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This paper presents a methodology of parallel implementations design that starts with abstract sequential descriptions of complex systems when no any parallel solutions have been taken and solves dynamically at real input data very complex tasks that are typical for system-level design. Critical path and parallelization potential based profiling of large sequential algorithms on data flow execution graphs is the kernel of methodology that enables to search for optimal (sub-optimal) parallel implementation solutions at very abstract level of design flow. Experimental results obtained on the critical path and parallelization potential based profiling of MPEG4 video codec and subsequent performance analysis of possible parallel implementations prove usefulness and effectiveness of the developed methodology and tool.

The search for energy efficiency in the design of embedded systems is leading toward CPUs with higher instruction-level and data-level parallelism. Unfortunately, individual applications do not have sufficient parallelism to keep all these CPU resources busy. Since embedded systems often consist of multiple tasks, task-level parallelism can be used for the purpose. Simultaneous multi-threading (SMT) proved a valuable technique to do so in high-performance systems, but it cannot be afforded in system with tight energy budgets. Moreover, it does not exploit data-level parallel hardware, and does not exploit the available information on threads.

We propose software-SMT (SW-SMT), a technique to exploit task-level parallelism to improve the utilization of both instruction-level and data-level parallel hardware, thereby improving performance. The technique performs simultaneous compilation of multiple threads at design-time, and it includes a run-time selection of the most efficient mixes.

We have applied the technique to two major blocks of a SDR (software-defined radio) application, achieving energy gains up to 46% on different ILP and DLP architectures. We show that the potentials of SW-SMT increase with SIMD datapath size and VLIW issue width.

Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy of memory system, which unlike others, lowers energy of refresh operation in DRAM. The approach is based on two key ideas: (1) DRAM-based flash cache that keeps dirty pages to reduce the number of accesses to flash memory; and (2) OS-controlled page allocation/aging to stop the refresh operations in banks, whose pages are clean and not accessed for a long time. Simulations show that by using this technique we can decrease the overall energy consumption of DRAM/flash memory on video applications by 8-26% while reducing the DRAM refresh energy by 59-74%.

We present a top-down technique to estimate the average dynamic power consumption of combinational circuits at the register transfer level. The technique also captures the power-delay characteristics of a given combinational circuit. It uses the principles of logical effort to estimate the variation in capacitance, and a combination of existing techniques to estimate the variation in activity, over the delay curve of operation of the circuit. The technique does not involve post-estimation characterization and is applicable across technology nodes. The estimated power obtained from our method shows good accuracy with respect to the power obtained from a commercial gate-level power estimation tool.

Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show that LSDL can provide more than 35% energy savings than CD with 25% switching activity at relaxed cycle times greater than 10.5 FO4.

We present a blackbox approach to model leakage currents of RTL data-path components. The model inputs are temperature, , body voltage of NMOS and PMOS and the bitvector at the input. Additionally, the model accepts a statistical Gaussian variation introduced by intra-die and systematic variation introduced by inter-die. Both variations can be given independently for each BSIM-level process parameter; in this work we evaluate variation of channel length, gate-oxide thickness and channel doping. Model output is the sum of subthreshold, gate, and pn-junction leakage. The evaluation of an RT component can be done in milliseconds and the result for the 45 and 65 BPTM technology is within 2% against single BSIM4.40 evaluation and within 5% against statistical BSIM4.40 evaluation assuming 1% variation of the process parameters.

We present a novel technique to accurately describe the leakage power in CMOS nanometer Integrated Circuits (ICs) considering process variations. The model predicts a leakage power increment due to process variations with high accuracy. It is shown that leakage increases considerably as channel length variations become larger due to technology scaling. The present work also describes accurately the dependence of leakage dispersion with process variations. The model developed shows that, even if channel length variations are kept small the leakage dispersion is considerably large. Finally, the concept of “Hot Gates” (HGs) is introduced, showing that HGs will be an important reliability factor in near future nanometer technologies.

In this work is presented an automated method for adjusting two-level cache memory hierarchy in order to reduce energy consumption in embedded applications. The proposed heuristic, TECH-CYCLES (T C E H CYCLES), consists of making a small search in the space of configurations of the two-level cache hierarchy, analyzing the impact of each parameter in terms of energy and number of cycles spent for a given application. Experiments show an average reduction of about 41% in the energy consumption by using our heuristic when compared with the existing heuristic (TCaT), also for two-level caches. Besides the energy improvement, this method also reduces the number of cycles needed to execute a given application by about 25%. In order to validate the proposed heuristic, twelve benchmarks from the MiBench suite have been used.

The main memory is one of the most energy-consuming components in several embedded system. In order to minimize this memory consumption, an architectural solution is recently adopted. It consists of multi-banking the addressing space instead of monolithic memory. The main advantage in this approach is the capability of setting individually banks in low power modes when they are not accessed, such that only the accessed bank is maintained in active mode. In this paper we investigate how this power management capability built into modern DRAM devices can be handled for real-time and multitasking applications. We aim to find, at system level design, both an efficient allocation of application’s tasks to memory banks, and the memory configuration that lessen the energy consumption: number of banks and the size of each bank. Results show the effectiveness of this approach and the large energy savings.

An adiabatic charge-pump based charge recycling design was proposed in [1]. It was shown to save upto 15% energy on several DSP systems with no performance loss. In this paper, we illustrate new charge source multiplexing techniques that are especially targeted towards SRAM arrays. The trigger control mechanism for charge sharing, additionally, can be derived from the application level characteristics rather than from circuit level attributes. These two methods help minimize the charge sharing energy dissipation. The SPICE level simulation results show that the proposed scheme reduces energy consumption in L2 caches by 24.9% with no performance loss.