Catálogo de publicaciones - libros

In this communication, different techniques to improve the resistance to Differential Power Analysis (DPA) attacks of precharged busses are discussed. These statistical attacks rely on the observation of the power consumption, and are very effective in recovering confidential information that are stored or processed in SmartCards running cryptographic algorithms. Accordingly, a few techniques to improve the information security by reducing the effectiveness of DPA attacks are discussed. These techniques are statistically analyzed and compared in terms of DPA resistance, power and area overhead. Finally, these techniques are mixed to improve the robustness to DPA attacks. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the discussed techniques.

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual-rail logic is carried out. The result of this investigation, performed on 130nm process, is a formal identification of the design range in which dual-rail logic can be considered as robust.

The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.

The scaling of CMOS technology is coming soon to an end, and yet it is unclear whether CMOS devices in the 10-20 nanometer range will find a useful place in semiconductor products. At the same time, new silicon-based technologies (e.g., silicon nanowires) and non-silicon based (e.g., carbon nanotubes) show the promise of replacing traditional transistors. In this scenario, there are multiple challenges to face, like the production of nanoscale CMOS with reasonable yield and reliability, the creation of newer circuit structures with novel materials as well as the mixing and matching of older and newer technologies in search of a good balance of costs and benefits.

As leakage power and total power is a more and more dramatic issue in very deep submicron technologies, this paper explores new design methodologies for designing leakage tolerant digital architectures, based on architectural parameters like activity, logical depth, number of transitions for achieving a given task and total number of gates. Various architectures for a same logic function are compared at very low Vdd and Vth that define the optimal total power consumption of each architecture. The first proposed design method selects the best architecture out of a set of architectures (baseline, sequential, parallel, pipelined, etc..) at optimal Vdd and threshold voltages Vth, while a second design method takes Vdd and threshold voltages Vth as given constraints.

Asynchronous design is emerging as a practical alternative to synchronous design for both low power and high performance applications. Moreover, ASIC flows that support asynchronous design are becoming complete, including many that leverage existing front-end and back-end synchronous-oriented tools. This talk will review the different design styles and flows and highlight some of the on-going commercialization efforts in this area. Special attention will be paid to the single-track circuit families developed at USC that provide ultra high performance and low power characteristics. We will review the associated standard-cell libraries and flows that have been developed as well as the recent chip design efforts that demonstrate the benefits of this technology.

The deep sub-micron technologies of today present us with new opportunities and challenges. On one hand the level of integration and available process options enables the development of fully integrated high performance systems (digital, mixed signal and RF) , while on the other hand we have the challenge of designing with increasing manufacturing variation and new electrical /reliability effects to consider. New design tools and methodologies are required. Looking to the past and even the present can give clues for the direction to take for the future. This talk , will describe through concrete examples the challenges overcome in developing design platforms for volume manufacture in the most recent technology nodes, including discussing the most imminent challenges to solve to maximize the benefit from forthcoming technologies.

The power density has been steadily increasing with technology scaling, while die sizes have not shrunk accordingly due to cost reasons. The combination of these two trends has resulted in a constant increase in power consumption for integrated circuits. This situation further worsens when we also look at the application from its power/performance requirements point of view. Most of the products, that consumers want, already have hard power budgets as either the final device is expected to run on batteries for weeks or due to the increasing cost of energy. These trends lead to power as our primary foe along the path dictated by Moore’s law.

Low power management is a critical design front for complex wireless systems. Not only different natures of the blocks required different power supplies (1.5V, 2.5V). Blocks are switched on and off sequentially during the duty to save power. A simple connection error can damage or destroy a block. Top level verification of such a complexity is required to guaranty the quality and the robustness of the final product.

As the electronics industry continues its move towards advanced process geometries, significant challenges have emerged that cannot be met by the existing design infrastructure. Across the design and manufacturing chain, a need has emerged for a power-aware infrastructure that will benefit design teams; ASIC, library, IP, and tool vendors; equipment providers; and manufacturing facilities alike.