Catálogo de publicaciones - libros

Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embedded architectures.

The grade of abstraction (specification level) for designing digital circuits has risen in the recent years from RT over algorithmic up to system level. An ambitious challenge of the EDA is to provide an efficient design space exploration with design-solutions comparable to hand-crafted optimi sations. The accuracy of the legal design space directly influences the efficiency of automatically generable designs. Current Design-Tools do not exploit the freedom that is enabled by array data-flow analysis (ADFA). This paper shows the impact of our ADFA on behavioural synthesis and estimation for the metrics execution-time, area, and energy. Data-flow intensive benchmarks show improvements of up to 12% less energy and 30% less execution-time while area varies by ± 15%.

This paper analyzes the issues that face digital circuit design methodologies and tools which address energy-efficient digital circuit sizing. The best known techniques for resolving these issues are presented, along with the sources of error. The analysis demonstrates that input slope independent models for energy and delay and stage based optimization are effective for analyzing and optimizing energy-efficient digital circuits when applied correctly.

A multiple stage adaptive bias error amplifier has been developed for a linear voltage reducer that should regulate for a very large and continuous supply-voltage range between 1.2 and 3.6 V. It uses both the 3.3 V high voltage transistors available in the considered generic 0.18 m logic process to allow above 1.8 V functioning and the normal transistors needed to reach the desired performance at the lowest supply voltages. The proposed multiple stage approach solves the contradictory requirements for low and high supply voltages, reduces the amplifier power consumption to less than 1.35 % of the load current and shows good regulator stability in spite of an increased number of poles.

This paper analyzes energy minimization of digital circuits operating at supply voltages above threshold and in the sub-threshold region. Circuit sizing and supply-voltage selection are simultaneously analyzed to determine where the minimum energy solution occurs. In this work we address the effects of architectural modifications on the design choices in different regions of operation. Two new architectural parameters are introduced that can be used for fast design comparison in the low power region of operation.

Considering the complexity of the future 4G telecommunication systems, power consumption management becomes a major challenge for the designers, particularly for base-band modem functionalities. System level low-power policies which optimize dynamically the consumption, achieve major power savings compared to low level optimisations (e.g gated clock or transistor optimisation). We present an innovative power modeling methodology of a 4G modem which allows to accurately qualify such low power solutions. Then, we show the energy savings attended by these power management methods considering silicium technology.

In this work, we develop simple yet very effective bus encoding schemes that dramatically reduce both self and coupling transition activity in common DSP signals. We show that, efficient low-power codes must cope with the different statistical characteristics of the most and least significant bits. On one hand, the high correlation in the most significant bits can be exploited by employing a simple non-redundant code. On the other hand, Bus Invert based codes are very efficient when applied only on the poorly correlated uniformly distributed least significant bits. The latter should not be employed on the most significant bits in order to preserve their high correlation. Additionally, we show that low-power codes can be easily compared by means of a simple graphical method.

This paper evaluates the feasibility of on-chip transmission-line interconnect at 45nm CMOS technology. Circuit performances tend to depend heavily on global interconnects, and power and delay of global interconnects are increased due to the miniaturization of process technology. On-chip transmission line has been proposed, which can improve such the large delay and large power consumption of the long RC interconnects. The improvement has been evaluated only for a single interconnect. In this paper, the total power reduction of the entire circuit is evaluated for 45nm technology, which is based on the measurement results at 180nm technology. As an example, the power consumption of global interconnects is improved by 6.6% on a circuit designed for 45nm process.

This paper presents two high-throughput, low-latency converters that can be used to convert synchronous communication protocol to asynchronous one and vice versa. These two hardware components have been designed to be used in Multi-Processor System on Chip respecting the GALS (Globally Asynchronous Locally Synchronous) paradigm and communicating by a fully asynchronous Network on Chip (NoC). The proposed architecture is rather generic, and allows the system designer to make various trade-off between latency and robustness, depending on the selected synchronizer. These converters have been physically implemented with the portable ALLIANCE CMOS standard cell library and the architecture has been evaluated by SPICE simulation for a 90nm CMOS fabrication process.

Increased Peak-to-Average Power Ratio (PAPR) is a serious drawback in an Orthogonal Frequency Division Multiplexing (OFDM) system, leading to inefficient amplification of the transmitted signal. Partial Transmit Sequences (PTS) approach is a distortionless PAPR-reduction scheme which imposes low additional complexity to the overall system. This paper introduces a new version of the PTS algorithm which selects weighting factors from a different set than the ones commonly used. Furthermore, this paper proposes a new PAPR estimation method that reduces the implementation complexity. The proposed architecture reduces the power consumption of the complete transmitter by up to 22% in comparison to OFDM systems where no PAPR reduction method is employed, depending on the power consumption of the power amplifier.