Catálogo de publicaciones - libros

The nested Miller frequency compensation (NMC) for multistage amplifiers is a well-known technique used to overcome the phase margin degradation due the low-frequency poles introduced by cascading stages. The NMC exploits both the Miller capacitance-multiplier effect and the pole-splitting action. In literature NMC capacitor sizing rules have been presented to design amplifiers characterised by a third-order Butterworth unity-gain closed-loop response. In the paper, the Authors show these criteria neglecting transistor parasitic capacitances, may lead to incorrect amplifier behaviour when small load capacitances have to be driven. A developed model, allowing better pole location estimation, is also presented.

In modern electronic products the increasing demand for greater performance and throughput often dictates the need for higher operating frequencies. The fundamental operating frequencies of microprocessors, consumer electronics, and networking applications in use today have exceed hundreds of megahertz and are rapidly approaching, and in several cases exceeding, the gigahertz range, and with the current and future technology scaling trends will continue to raise. However, with such increment in frequency often comes an increase in electromagnetic interference (EMI). Therefore, EMI and radiated emissions are a major problem for high-speed circuit and package designers, which is likely to become even more severe in the future. However, until recently, IC and package designers did not give much consideration to electromagnetic radiated emission and interference in their designs. The enforcement of strict governmental regulations and international standards in the automotive domain are driving new efforts towards design solutions for electromagnetic compatibility (EMC). In order to avoid costly design re-spins, EMC compliance must be validated before fabrication with the support of EMC-aware CAD tools and design guidelines. In this work, we propose an effective and practical approach to assess the spectral content of on-chip signals, which are one of the most detrimental sources of electromagnetic (EM) emissions, and provide valuable guidelines to focus the design efforts on reducing the high-frequency harmonics.

In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effect and the scaling factors that use the information of physical architecture. The proposed approach is very useful to be combined with memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into commercial power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

The advance in semiconductor technologies has increased the number of transistors on a die, resulting in the continuous improvement in microprocessor performance. However, the increase in power consumption and hence in power density is about to stop the progress in microprocessor performance. While supply voltage reduction is commonly known as an effective technique for power savings, it increases gate delay and thus causes performance degradation. The increasing transistors can be utilized for maintaining performance while reducing power consumption. We are considering a speculative multithreaded execution on MultiCore processors. We propose to execute only the part of the program, which has the impact on program execution time, on power-hungry cores. In order to enable this, we divide the instruction stream into two streams. One is called speculation stream, which is the main part of a program and where speculation is applied. It is executed on power-hungry cores. The other is the verification stream, which verifies every speculation. It is executed on low-power cores. The energy consumption is reduced by the decrease in the execution time in the speculation stream and by the low-power execution in the verification stream. We call this technique Contrail architecture. The paper will present the energy efficiency of a Contrail processor based on detailed simulations.

In this work we will introduce an enhanced, -compatible adiabatic logic family based on a new diode element for charge recovery. This diode element uses bipolar transistors to reduce the diode forward voltage losses in existing charge recovery logic families allwoing the use at lower supply voltages. Based on this element the compatible, static adiabatic logic familiy is introduced.

This paper presents a framework for estimation of peak power dissipation in gate level circuits. This measure can be used to make architectural or design style decisions during the VLSI synthesis process. The proposed method first builds a symbolic event list for every possible input and uses this as the database for computing the peak power estimate. A novel heuristic search based method is presented which works on this symbolic event list to estimate peak power. Experimental results on ISCAS’89 benchmarks demonstrate the proposed method to be effective on moderately large circuits.

Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. However, its performance analysis is relatively complex. In fact, the handshaking protocol strongly influences the performance of the pipelined architectures. This paper introduces verified Standard-Logic schematics for QDI asynchronous latches and analyzes their characteristics. Buffering capacity and protocol gain are defined and analyzed. Based on this analysis, reduced performance equations are first introduced. By means of the dependency graphs, a new formal method is then proposed to analyze the performance of asynchronous linear-pipeline. This methodology is used to derive general equations for each latch type. Contrarily to previously proposed methods, this method can be applied to any asynchronous linear-pipeline without restrictions on its functional block delays. Therefore, the contributions of this paper enable the designers to understand the benefits brought by the different asynchronous latches, to compare them and make the right choice according to their design constrains....

In this communication, a model of the precharged bus power consumption in digital VLSI circuits is developed. This model is used to analytically evaluate the result of a multi-bit Differential Power Attack (DPA) to the address bus of cryptographic ICs running the DES algorithm. This attack to the address bus is based on the observation of its power consumption, and is well known to be a major threat to the security of the confidential information stored or processed by SmartCards. The results allow to achieve a quantitative model of the DPA attack effectiveness, and is useful as a theoretical basis to understand the trade-offs involved in DPA attacks. This deeper understanding is useful to identify the cases where a SmartCard under attack is weaker with respect to DPA attacks, i.e. when the power consumption reveals the maximum amount of information. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the model and the underlying assumptions.

This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.

Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. The subthreshold leakage current increases exponentially in deep-submicron processes and hence is a crucial factor in scaling down designs. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, a novel technique that achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) for any CMOS complementary circuit is presented. It involves voltage balancing in the PUN and PDN paths using sleep transistors. Experimental results show significant leakage power savings (average of 54X at a temperature of 27C) in CMOS circuits employing this sleep circuitry when compared to standard CMOS circuits. At any given temperature, using our methodology the leakage power loss increases linearly with increasing circuit complexity and hence the leakage loss can be predicted for any CMOS complementary circuit.