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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings

Johan Vounckx ; Nadine Azemard ; Philippe Maurine (eds.)

En conferencia: 16º International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) . Montpellier, France . September 13, 2006 - September 15, 2006

Resumen/Descripción – provisto por la editorial

No disponible.

Palabras clave – provistas por la editorial

Theory of Computation; Logic Design; Processor Architectures; System Performance and Evaluation; Arithmetic and Logic Structures; Memory Structures

Disponibilidad
Institución detectada Año de publicación Navegá Descargá Solicitá
No detectada 2006 SpringerLink

Información

Tipo de recurso:

libros

ISBN impreso

978-3-540-39094-7

ISBN electrónico

978-3-540-39097-8

Editor responsable

Springer Nature

País de edición

Reino Unido

Fecha de publicación

Información sobre derechos de publicación

© Springer-Verlag Berlin Heidelberg 2006

Tabla de contenidos

The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing

Yijun Liu; Steve Furber; Zhenkun Li

Power consumption has become one of the most important concerns in the design of embedded processor; the power dissipation of microprocessors grows rapidly as the development of CMOS technology packs more transistors per unit area. However, the potential for further power saving in microprocessors with a conventional architecture is limited because of their unified architectures and mature low-power techniques. An alternative approach to save power is proposed in this paper — embedding a dataflow coprocessor in a conventional RISC processor. The dataflow coprocessor is designed to execute short code segments, such as small loops, function calls and long equation evaluations, very efficiently. We demonstrate a factor of 7 improvement in power-efficiency over current general-purpose processors. Dataflow techniques are not new, but we apply the concept to address a new problem — to improve the power-efficiency of conventional processors.

- Session 10 – Reconfigurable and Programmable Devices | Pp. 425-438

Optimization of Master-Slave Flip-Flops for High-Performance Applications

Raúl Jiménez; Pilar Parra; Javier Castro; Manuel Sánchez; Antonio Acosta

The design of high-performance master-slave flip-flops is of crucial importance in modern VLSI. The optimization of existing structures is necessary when the requirements of the flip-flop is for low-power, high-speed or low-noise applications. In this work, the optimization via transistor sizing of a well-known master-slave flip-flop is investigated. A detailed analysis of the flip-flop structure provides information useful for optimization, giving an optimum solution for an specific high-performance application.

- Poster 1 | Pp. 439-449

Hierarchical Modeling of a Fractional Phase Locked Loop

Benjamin Nicolle; William Tatinian; Jean Oudinot; Gilles Jacquemod

The aim of this study is to provide a multi level VHDL-AMS modeling of an analog Phase Locked Loop (PLL). Three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. The characteristic parameters of the PLL, such as the settling time, overshoot, voltage variations linked to charge pump architecture and final voltage are extracted from the intermediate level.

- Poster 1 | Pp. 450-457

Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs

Régis Roubadia; Sami Ajram; Guy Cathébras

This paper introduces two low power design techniques to improve both the jitter and phase noise of PLL frequency synthesizers used in ASICs. These techniques focus on the noise current reduction in wideband ring VCOs. Two PLLs embedding such VCOs were implemented, in 0.18 and 0.13 CMOS technologies, under 1.8 and 1.2 supply voltages respectively. The maximum improvement was observed for a 1.8 PLL running at 160MHz and consuming 1.6mW, which phase noise was reduced from -81.4dBc/Hz to -88.4dBc/Hz.

- Poster 1 | Pp. 458-467

Statistical Characterization of Library Timing Performance

V. Migairou; R. Wilson; S. Engels; N. Azemard; P. Maurine

With the scaling of technology, the variability of timing performances of digital circuits is increasing. In this paper, we propose a first order analytical modeling of the standard deviations of basic CMOS cell timings. The proposed model is then used to define a statistical characterization protocol which is fully compliant with standard characterization flows. Validation of this protocol is given for a 90nm process.

- Poster 1 | Pp. 468-476

Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors

Oğuz Ergin

Register file is a hot spot in contemporary microprocessors. As the number of instructions present in the processor at a given time increases, the size of the register file increases and it becomes a more important source of power dissipation inside the processor. Therefore it is important to pursue techniques that reduce the energy dissipation of register files. In this paper we present a technique that exploits the narrowness of the produced and consumed values in order to reduce the dynamic energy dissipation of the register file. Our technique results in 20% energy reduction in the integer register file on average.

- Poster 1 | Pp. 477-485

Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS

Saihua Lin; Hongli Gao; Huazhong Yang

By using output control and MTCMOS techniques, we propose two low power low clock swing D flip-flops. Experimental results show that the leakage power of the proposed flip flops can be reduced more than an average of 59% in standby mode and in active mode the total power consumption can be reduced more than an average of 53% while the delay time stays the same. It is also show that the proposed D flip-flops can work even when the clock swing is nearly as low as V/3, though the delay time is much increased.

- Poster 1 | Pp. 486-495

Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations

Jürgen Rauscher; Hans-Jörg Pfleiderer

In this paper the influence of parameter variations to the effect of power supply noise damping in digital CMOS circuits is investigated. Splitting up the power supply path and using different additional resistors in each path combined with a slight increase of the off-chip supply voltage is found to reduce significantly power supply noise. The damping resistors are optimized using a simulated annealing schedule for the worst-case current waveform. The dependency of this approach to current waveform variations and an increased resistance due to electromigration or a higher operating temperature is examined.

- Poster 1 | Pp. 496-503

Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling

Saihua Lin; Huazhong Yang

In this paper, an ABCD modeling approach is proposed to model the inductive and capacitive coupling effect between the interconnect lines in DSM circuits. Then, a physical aspect model is introduced to analyze the worst case crosstalk noise effect on the delay and rise time of the driver. It is observed that the inductive coupling effect can have a great effect on the timing characteristic of the interconnect line. Experimental results show that the method proposed in this paper differs from the HSPICE simulation with an average error less than 2.5% for both the 50% delay and the rise time.

- Poster 1 | Pp. 504-513

A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors

Guadalupe Miñana; José Ignacio Hidalgo; Oscar Garnica; Juan Lanchares; José Manuel Colmenar; Sonia López

This paper presents a hardware technique to reduce both the static and dynamic power consumption in Functional Units of a 64-bit superscalar processor. We have studied the instructions that require an adder and we can conclude that, in 64-bit processors, there are many instructions that do not require a 64-bit adder, and that by knowing the type of operation we can also know what adder type this instruction requires. This is due that there are some types of instruction where one of the two source operands is always narrow. Our approach is based on substituting some of the 64-bit power-hungry adders by others of 32-bit and 24-bits lower power-consumption adders, and modifying the protocol in order to issue as much instructions as possible to those low power-consumption units incurring in a negligible performance penalty. We have tested four different configurations for the execution units in order to find which one obtains a higher reduction on power-consumption, preserving the performance of the processor. Our technique saves between 38,8% and a 54,1% of the power-consumption in the adders which is between 16,6% and a 23,1% of power-consumption in the execution units. This reduction is important because it can avoid the creation of a hot spot on the functional units.

- Poster 2 | Pp. 514-523