Catálogo de publicaciones - libros

The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a progressive refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the progressive refinement of hierarchical designs.

Crosstalk analysis has become a significant part of the design cycle of high performance processors in nanometer technologies. In this paper we demonstrate that current crosstalk analysis techniques that ignore the degrading effect of multiple crosstalk events on receiver noise rejection curve filter significant number of true violations. We also demonstrate that techniques that take into account the multiple crosstalk events with traditional receiver modeling result in large number of false violations. We propose improved crosstalk analysis techniques that are multiple noise event aware (MNEA) with minimal changes to existing crosstalk analysis. We also propose enhancements to existing receiver models so they can be used with the MNEA analysis resulting in reduction of number of false violations by 68%-98% while guaranteeing identification of all true violations.

The manufacturing defect in the interconnect lines can lead to various electrical faults, defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the DSM chips. In this paper we describe the line defect-based-crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs approximately by ±5% respectively.

This paper proposes body-bias generator for leakage power reduction of digital logic circuits which operates at low supply voltage of 0.5V. The proposed circuit adopts double charge pumping scheme to enhance the pumping gain. The proposed circuit is fabricated using 0.13 m CMOS process and measurement result demonstrates stable operation with body-bias voltage of -0.95V. We apply the proposed circuit to 64-bit carry look-ahead adder to demonstrate its performance. We report that the leakage power of 64-bit carry look-ahead adder can dramatically be reduced by adopting proposed substratebias generator. The estimated leakage power reduction is 90% (T=75°C).

In this paper we present the effect of process variations on the design of clocked storage elements. This work proposes to use the Energy-Delay space analysis for a true representation of the design trade-offs. Consequently, this work also shows a comparison of clocked storage elements under a specific set of system constraints for typical corner design and high yield corner design. Finally, we show that designing for high yield can affect the choice of topology in order to achieve energy efficiency.

IR-drop problem is becoming more and more important. Previous works dealing with power/ground (P/G) network peak current reduction to reduce the IR-drop problem only focus on synchronous sequential logic circuits which consider the combinational parts as unchangeable [4],[5]. However, some large combinational circuits which work alone in one clock cycle can create large current peaks and induce considerable IR-drops in the P/G network. In this paper, we propose a novel combinational circuit IR-drop reduction methodology using Switching Current Redistribution (SCR) method. A novel combinational circuit partitioning method is proposed to rearrange the switching current in different sub-blocks in order to reduce the current peak in the P/G network, while circuit function and performance are maintained. Experimental results show that, our method can achieve about 20% average reduction to the peak currents of the ISCAS85 benchmark circuits.

In adiabatic circuits, the energy dissipation occurs during every cycle, as output nodes are always charged and discharged by power-clocks. This paper presents a low-power register file based on adiabatic logic with power-gating techniques. N-type adiabatic drivers with power-gating schemes are used to drive read bit and read data lines, while P-type adiabatic drivers with power-gating schemes are used to drive write bit lines and power storage cells. The write and read drivers for driving bit and word lines can be switched off to reduce energy losses during idle times. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. SPICE simulations indicate that the proposed register file achieves considerable energy savings over CMOS implementation.

In this paper, we propose a new technique for higher circuit speed without increase in leakage current by using active body-bias controlling technique. Conventional body-bias controlling techniques face difficulties, such as long transition time of body voltage and large area penalty. To overcome these issues, we propose a Charge Recycling Active Body-bias Controlled (CRABC) circuit scheme on SOI which enables quick control of body voltage by using simple additional circuit. The SPICE simulation results have shown that CRABC shortens delay time by 20 %, and transition time for controlling body-bias by 98 %.

A novel approach for efficient implementation of applications onto reconfigurable architectures is introduced. The proposed methodology can applied both for designing an interconnection architecture as well as for making a thermal-aware placement. In the first case, the dominant parameters that affect performance and energy (segment length and switch boxes) are examined. This approach is based on finding the optimal wire length and then making exploration in order to determine the appropriate combination of multiple switch boxes. In the second case, a new technique for thermal-aware placement is introduced. The main goal of this technique is to spread out the power consumption across the whole device, as well as to minimize it. Both of the methodologies are fully-supported by the software tool called EX-VPR. For the purposes of this paper, the Energy× Delay Product (EDP) is chosen as selection criterion for the optimal interconnection network, while the total power consumption is the criterion for the thermal-aware routing. For the designing of the interconnection network we achieved EDP reduction by 45%, performance increase by 40% and reduction in total energy consumption by 8%, at the expense of increase of channel width by 20%. On the other hand, for the thermal-aware approach, we spread the heat and power across the whole FPGA, while we achieve about 20% reduction in total power consumption. In this case, the penalty in channel width is about 10%.

Today and more tomorrow, electronic system design requires being concerned with the power issues. Currently, usual design tools consider the application power consumption after RTL synthesis. We propose in this article a FPGA design flow which integrates the power consideration at the early stages. Thus, the designer determines quickly the algorithm and architecture adequacy which respects the design specifications and the power budget.