Catálogo de publicaciones - libros

High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the implementation of the thermal management scheme as a secondary problem.

In this work we focus on the implementation issues involved in the implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of . We demonstrate the feasibility of the VDB-based methodology, and compare different implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).

A new operation mode for a lateral unified-complementary BiCMOS (hereafter abbreviated as U-CBiCMOS) buffer driver based on a partially depleted CMOS/SOI process is proposed. The scheme utilizes a gated npn or pnp BJT inherent to a n- or p-channel MOSFET. Forward current is applied to the base terminal of the channel MOSFET, with a normal pull-up or pull-down MOSFET as a current source, where each drain terminal is connected to the corresponding base terminal of the buffer. A new logic scheme is designed to feed an input signal to the gates of the pull-up and pull-down MOSFETs, rather than to those of the n- and p-channel MOSFETs as in our previous work, while also keeping both the n- and p-channel MOSFETs inactive and activating either the lateral npn or pnp BJT. A clock generator composing of the ring oscillator with a 21-stage CMOS inverter driven by the U-CBiCMOS buffer driver is designed. Circuit simulation using 0.35m BSIM3v3 model parameters for the MOSFETs and a current gain of = 100 for the BJTs revealed the speed of the U-CBiCMOS buffer driver to be more than 4 times faster than that of an equivalent 4-stage CMOS (4SCMOS) inverter designed on the basis of logical effort for driving a load capacitance of 1.417 pF at = 1 V.

This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. The cell libraries come in fixed threshold – high V for good standby power and low V for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.

Real-time video encoding often demands hardware motion estimators, even when fast search algorithms are adopted. With the widespread usage of portable handheld devices that support digital video coding, low power consideration becomes a central limiting constraint. Consequently, adaptive search algorithms and special hardware architectures have been recently proposed to perform motion estimation in portable and autonomous devices. This paper proposes a new efficient carry-free arithmetic unit to compute the minimum distance in block matching motion estimation. The operation of the proposed unit is independent of the adopted search algorithm and of the used prediction error metric, simultaneously speeding up motion estimation and significantly reducing the power consumption. Moreover, its low latency is particularly advantageous when partial distance techniques are applied to further reduce the power consumption. Experimental results show that the proposed unit allows to reduce the computation time in about 40% and it consumes 50% less power than commonly adopted architectures.

Wireless sensor networks (WSNs) gained increasing interests in recent years; since, they allow wide range of applications from environmental monitoring, to military and medical applications. As most of the sensor nodes (a.k.a. motes) are battery operated, they have limited lifetime, and user intervention is not feasible for most of the WSN applications. This study proposes a technique to reduce the energy dissipation of the processor component of the sensor nodes. We utilize a tiny cache-like structure called MoteCache between the CPU and the SRAM to cache the most recently used data values as well as to filter silent-store instructions which write values that exactly match the values that are already stored at the memory address that is being written. A typical WSN application may sense and work on constant data values for long durations, when the environmental conditions are not changing rapidly. This common behavior of WSN applications considerably improves our energy savings. The optimal configuration of MoteCache reduces the total node energy by 24.7% on the average across a variety of simulated sensor benchmarks. The average lifetime of the nodes is also improved by 46% on the average for processor-intensive applications. Using the proposed technique, the lifetime of the nodes that run communication-intensive applications, such as TinyDB and Surge, is also improved as much as 14%.

This paper presents a comparison of two engines providing encryption and authentication of data exchanged between a System on Chip (SoC) and its external memory. The first engine is based on a generic composition scheme, meaning that each required security service, confidentiality and authentication, is guaranteed by a dedicated algorithm i.e. respectively AES (Advanced Encryption Standard) and CBC-MAC (Message Authentication Code). The second one, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), uses AES encryption to provide both properties to data by adding the authentication capability to block cipher. Performance evaluations show that our scheme PE-ICE always outperforms the combination of AES encryption and CBC-MAC.

Considering the SmartCards (SC) family, two products types can be defined: contact and contactless ones. For contactless SC, analysis of power consumption is essential. While functioning, energy for these products is supplied by electromagnetic waves and value of stored energy depends directly on the distance between the emitter and the card. Then, for each defined product operations, and at any time, the stored energy must be higher than the required energy. If not, the product will not operate correctly. This paper presents a methodology to survey the dynamic power of contactless SC by current analysis, and so to verify safe operation mode of the product.

A new scheme namely variable monitoring period scheme (VMP) is proposed to reduce the power consumption of a battery management system (BMS) used in implantable biomedical application devices. Self tuning level of reference voltage is used to make reference voltage flattened. Proposed circuit is fabricated in Samsung 0.35m CMOS process and experimental results show that it consumes only 100nW@1.5V and total variance of reference voltage is reduced to be only 3mV over entire supply voltage range.

Timing analysis of complex state-of-the-art designs demands efficient algorithms able to cope with design complexity. Exploring the hierarchical information generally encountered in complex designs became mandatory to perform functional timing analysis (FTA) in acceptable execution times. Although several hierarchical FTA approaches exist, only path-based hierarchical FTA is able to identify global critical paths, thus helping designers in the optimization task. In this paper we propose two versions of path-based hierarchical FTA strategies. These versions are compared to flat-mode FTA and to commercial FTA tools that operate in hierarchical mode.

Repeater insertion is one of the most effective techniques to reduce the propagation delay related to long interconnects.

However, its application to deep submicron technologies leads to sub-optimal results if the traditional sizing rules are followed.

In the paper the Authors show the behaviour of deep-sub micron devices may differ significantly from the conventional one due to transistor parasitic capacitance. As a consequence, well-exploited assumption as linear relationship between channel width and output conductance of the CMOS gate start to fails, as well as it does optimisation techniques based upon them. A developed formula for buffer sizing is proposed based on a simplified model allowing MOS parasitic to be taken into account. Up to 50% area and leakage power saving can be obtained.