Catálogo de publicaciones - libros

Nowadays, embedded consumer devices execute complex network and multimedia applications that require high performance and low energy consumption. For implementing complex applications on Network-on-Chips (NoCs), a design methodology is needed for performing exploration at NoC system-level, in order to select the optimal application-specific NoC architecture. The design methodology we present in this paper is based on the exploration of different NoC characteristics and is supported by a flexible NoC simulator which provides the essential evaluation metrics in order to select optimal communication parameters of the NoC architectures. We show that it is possible with the evaluation metrics provided by the simulator we present, to perform exploration of several NoC aspects and select the optimal communication characteristics for NoC platforms implementing network and multimedia applications.

In this paper we propose a complete system energy model based on non-intrusive measurements. This model aims at being integrated in fast cycle accurate simulation tools to give energy consumption feedback for embedded systems software design. Estimations takes into account the whole system consumption including peripherals. Experiments on a complex ARM9 platform show that our model estimates are in error by less than 10% from real system consumption, which is precise enough for source code application design, while simulation speed remains fast.

We present an innovative general purpose architecture for the parallelization of nested loops in reconfigurable architectures, in the effort of achieving better execution times, while preserving design flexibility. It is based on a new load balancing technique which distributes the initial nested loop’s workload to a variable user-defined number of Processing Elements (PEs) for execution. The flexibility offered by the proposed architecture is based on “algorithm independence”, on the possibility of on-demand addition/removal of PEs depending on the performance-area tradeoff, on dynamic reconfiguration for handling different nested-loops and on its availability for any application domain (design reuse). An additional innovative feature of the proposed architecture is the hardware implementation for dynamic generation of the loop indices of loop instances that can be executed in parallel (dynamic scheduling) and the flexibility this implementation offers. To the best of our knowledge this is the first hardware dynamic scheduler, proposed for fine grain parallelism of nested loops with dependencies. Performance estimation results and limitations are presented both analytically and through the use of two case studies from the image processing and combinatorial optimization application domains.

Complex application specific SoC are often based on the Network-on-Chip (NoC) approach. NoC are under investigation since several years and many architectures have been proposed. Generic NoC are often proposed with their synthesis tool in order to rapidly tailor a solution for a specific application implementation. The optimized mapping of cores on a NoC and the optimized NoC configuration in terms of topology, FIFO and link sizes for instance is a new research area which is investigated deeply now. Validation and evaluation of solutions is often conducted through simulations. Comparisons between proposed optimization approaches is difficult as they use their own evaluative application. Benchmarking is a classical solution to normalize comparisons. We are proposing in this paper a complete design flow which allow to make an automatic Algorithm Architecture Adequation (AAA) onto a NoC architecture. This flow is based on a SystemC model simulation at TLM level. We illustrate these design flow with a benchmark of an 4G radiocommunication application.

As a critical technology in the embedded system nowadays, program code compression can improve the code density and reduce the power consumption. Especially for the Transport Triggered Architecture (TTA), the long instruction word is one of the key problems to degrade the processor performance. In this paper, with the analysis to the spatial locality of the data transports, a template vertical dictionary-based program compression scheme is proposed. It not only efficiently eliminates the redundant empty slots as well as the invalid long immediate encodings, but also applies the vertical dictionary-based compression at the slot level. The experiment shows that this scheme achieves the compression ratio of 32.3%, especially corresponds to the tiny dictionary size. Then, the effects on area and power consumption are also measured. The total area of the processor core and the local instruction memory could be reduced by about 29% and power consumption by nearly 25% respectively.

This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor based on a reasonable power metric to guarantee accurate comparison. Apart from that, we also compare the design effort between synchronous and asynchronous implementations.

Assigning computational elements to low supply voltages can reduce dynamic power dissipation, but increase execution delays. The problem of reducing dynamic power consumption by assigning low supply voltages to computational elements off critical paths is NP-hard in general. It has been addressed in the case of combinational designs. It becomes more difficult in the case of clocked sequential designs since critical paths are defined relative to the position of registers. By repositioning some registers, some computational elements could be moved from critical paths, and hence their supply voltages can be scaled down. In this paper, we propose a polynomial time algorithm to determine solutions to this problem in the case of clocked sequential designs. Experimental results have shown that the proposed algorithm is able to significantly reduce dynamic power dissipation.

A low-power content addressable memory (CAM) with read/write and mask match ports is proposed. The CAM cell is based on the conventional 6T cross-coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre-charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18-m CMOS single poly and three layers of metals measuring a cell die area of 24.4375 m and a total silicon area of 0.269192 mm. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage.

In this paper, a power efficient 2K asynchronous SRAM is presented for embedded applications. The SRAM adopts a low swing write scheme, which greatly reduces the power dissipated by charging and discharging the bitlines. A small dual-rail decoder is proposed to compensate for the extra silicon area needed by the low swing write technique. The new SRAM is demonstrated to a factor of 4 improvement in power efficiency over a commercial SRAM macro. It also 30% faster than the commercial SRAM macro with only 3% area overhead.

This paper presents an extension of ALADIN for approximately calculating the current density and heat distribution of analog circuits. The tools are integrated into the ALADIN package, which allows designers to create analog circuit layouts automatically. The optimization is speeded up and the reliability of the design is improved. The benefit of ALADIN is demonstrated with the design of a linear power amplifier with ±1.5V power supply.