Catálogo de publicaciones - libros

The application of asynchronous circuit has been greatly restricted by reason of lacking effective technologies to test. Making use of the self-checking property of asynchronous control circuit, we may preferably solve this problem. In the paper, we put forward an improved, fail-stop David Cell, describe a way of designing self-checking asynchronous control circuits by the direct mapping technique, and propose the testing method for single stuck-at faults. The result shows that self-checking counterpart can be tested at normal operation speed and the area overhead is acceptable.

Recently, it has been proven that asynchronous circuits possess considerable inherent countermeasure against side channel attacks. In spite of these systems’ advantages for immune cryptography, because of the lack of automatic design tools and standard methods, exploiting such schemes faces difficulties. In this paper, a fully automated secure design flow and a set of secure library cells resistant to power analysis and fault injection attacks are introduced for QDI asynchronous circuits. In this flow a standard cell library has been introduced which has resistance to differential power analysis on faulty hardware attack. The results show that using this scheme is approximately 5.62 times more balanced than the best cells designed using previous synchronous balancing methods. To verify the efficiency of our presented flow we applied it to implementation of the AES cryptography algorithm. Also, this implementation shows a 2.8 times throughput improvement over the synchronous implementation using the same technology.

Dual rail logic is considered as a relevant hardware countermeasure against Differential Power Analysis (DPA) by making power consumption data independent. In this paper, we deduce from a thorough analysis of the robustness of dual rail logic against DPA the design range in which it can be considered as effectively robust. Surprisingly this secure design range is quite narrow. We therefore propose the use of an improved logic, called Secure Triple Track Logic, as an alternative to more conventional dual rail logics. To validate the claimed benefits of the logic introduced herein, we have implemented a sensitive block of the Data Encryption Standard algorithm (DES) and carried out by simulation DPA attacks.

This work presents an extensive study on the speedups achieved by mapping real-life applications in different instances of a hybrid reconfigurable system. The embedded heterogeneous system is composed by reconfigurable hardware units of different granularity. The fine-grain reconfigurable logic is realized by an FPGA, while the coarse-grain reconfigurable hardware by a 2-Dimensional array of word-level Processing Elements. Performance gains are achieved by mapping time critical loops, which execute slowly on the FPGA, on the Coarse-Grain Reconfigurable Array. An automated design flow was developed for mapping applications on the reconfigurable units of the platform. The conducted experiments illustrate that the speedups relative to an all-FPGA execution range from 2.33 to 6.42 being close to theoretical speedup bounds.

Scalable video allows to decode a single video stream, or part of it, at varying quality of service (QoS). Since the amount of calculations scales with the QoS, energy dissipation is expected to scale similarly. To investigate the relation between QoS and energy dissipation we actually measured the energy dissipation of a scalable video decoder implementation on an FPGA. The measurements show how dissipation effectively scales with QoS and indicate how energy can be saved by rescaling the QoS and reconfiguring the FPGA accordingly.

Today, wireless networks are becoming increasingly ubiquitous. Usually several complex multi-threaded applications are mapped on a single embedded system and all of them are triggered by a single wireless stream (which corresponds to the dynamic run-time behavior of the user). It is almost impossible to analyze these systems fully at design-time. Therefore, run-time information has also to be used in order to produce an efficient design. This introduces new challenges, especially for embedded system designers using a Direct Memory Access (DMA) module, who have to know in advance the memory transfer behavior of the whole system, in order to design and program their DMA efficiently. In this paper, we propose a mixed Hardware/Software optimization at system level. More specifically, we propose to adapt DMA usage parameters automatically at run-time based on online information. With our proposed optimization approach we manage to reduce the mean latency of the memory transfers while optimizing energy consumption and system responsiveness. We evaluate our approach using a set of real-life applications and real wireless dynamic streams.

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. They enable to eliminate design margins as well as to tolerate parameter variations. We are investigating canary logic, which we proposed as a promising technique that enables the typical-case design. Currently, we utilize the canary logic for power reduction by exploiting input variations, and its potential of 30% power reduction in adders has been estimated at gate-level simulations. In this paper, we evaluate how canary logic is effective for power reduction of the entire microprocessor and find 9% energy reduction.

Within the context of secure applications, side channel attacks are a major threat. The main characteristic of these attacks is that they exploit physical syndromes, such as power consumption rather than Boolean data. Among all the known side channel attacks the differential power analysis appears as one of the most efficient. This attack constitutes the main topic of this paper. More precisely, a design oriented modelling of the syndrome (signature) obtained while performing Differential Power Analysis of Kocher is introduced. As a validation of this model, it is shown how it allows identifying the leaking nets and gates during the logical synthesis step. The technology considered herein is a 130nm process.

It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves their timing and dynamic power characteristics. In this paper, the static power consumption of gates using this approach is addressed. When compared to conventional common body static CMOS, important static power enhancements are obtained. Accurate electrical simulation results reveals improvements up to 35% and 62% in NAND and NOR gates respectively.

This paper proposes to use a non conventional mode of operation to meet low voltage constraints: The moderate inversion. EKV 2.0 MOS model provides hand calculation applicable equations, while a BSIM3v3 simulation model is sufficiently accurate to design static circuits.

The self cascode structure studied with highlights of the EKV 2.0 MOS model is revealed to be linear with temperature from weak to strong inversion: simulation and experimental data are provided.

This self cascode linear with temperature voltage reference is the starting point of a new self biased current reference: An all in moderate inversion exemple is given, and simulation results are provided.