Catálogo de publicaciones - libros

A power-aware voltage-scheduling heuristic is presented for a hard real-time multi-processor system. Given a task graph, the offline component first allocates a certain percentage of worst-case execution units of some tasks to them as potions to be executed in a higher voltage. Once some path is speeded up, the rest of the offline component chooses and speeds up one of the paths sharing tasks with that path. The online component reclaims the slack, which occurs when some task actually finishes, to slow down the execution speed of its successor. Experimental results are finally provided to demonstrate the effectiveness of the proposed heuristic.

Power has become the most important candidate for optimization in today’s design. This is necessary for further functionality and processing capability to be added to the design. Standard cell design is the defacto standard for most IC designs. The other end of the spectrum is full custom design whose efficiency is very high, but with a large design time. In this paper we investigate the use of prototype module generators to improve the energy efficiency of the design over the standard cell design while trading off some design time. We investigate this on an interconnect intensive design namely the SIMD Shuffler which is one of the important parts of a low power embedded processor’s datapath. We show that using module generators, we can reduce the energy consumption of the shuffler by about 30%. We also show the possible research opportunities for filling in the further EDA tools for low power.

Until now, the great majority of research in low-power systems has assumed a convex power model. However, recently, due to the confluence of emerging technological and architectural trends, standard convex models have been invalidated for the proper specification of power models with different execution speeds. For example, the use of a shutdown energy minimization strategy to eliminate leakage power in multiprocessor systems results in a non-convex trade-off between power and speed. Non-convexity renders the majority of previous power management schemes, algorithms, and even basic theorems invalid. For instance, the main premise that one has to run continuously using a single speed in order to minimize energy consumption for constant computation requirements is not valid anymore.

We study techniques for energy minimization where the power versus speed curve has a non-convex shape. We first identify and quantify sources of non-convexity. Minimizing energy when the power-speed model is non-convex is an NP-complete problem, even in the canonical and simple case where a task is to execute a specified amount of computation without dependencies, in a given amount of time. We address this problem using a non-linear function minimization based approach and demonstrate that on average the new solution saves at least 40% more energy on industrial processors than techniques that follow the convexity paradigm. Then we address common real-time task scenarios where the power-speed model is non-convex. Specifically, we introduce a heuristic for scheduling tasks onto a multiprocessor system with a non-trivial start-up cost and compare its performance to our mixed integer linear programming (MIP) formulation. We experimentally compare our neighbors heuristic with the well-known average rate algorithm, and find that it results in a 106% improvement while being only 14% worse than the optimal MIP solution.

In this paper we present a new static power minimization technique exploiting the use of triple-threshold CMOS standard cell libraries in 90nm technology. Using static timing analysis, we determine the timing requirements of cells and place cells with low and standard threshold voltages in the critical paths. Cells with a high threshold voltage are placed in non-critical paths to minimize the static power with no overall timing degradation. From the timing and power analysis, we determine the optimal placement of high, standard and low threshold voltage cells. Using three different threshold voltages, an optimized triple-threshold 16-bit multiplier design featured 90% less static power compared to the pure low-threshold design and 54% less static power compared to the dual-threshold design.

In this paper, we present a new efficient methodology for power estimation of the well known family of asynchronous circuits, QDI circuits, at pre-synthesized level. Power estimation at high-level is performed by simulating the intermediate format of the design. This format consists of concurrent processes represented with CSP-Verilog. The number of and accesses on the ports of these concurrent processes are counted by analyzing the conditional and computational portion during the simulation which is the based of our estimation methodology. To verify the accuracy of our presented method we applied it to a Reed-Solomon decoder as the benchmark. The results show up to 15 % imprecision in comparison with the power measured by SPICE, also simulation speed is faster by factor of 7 compared to gate-level transition counting based methodology.

A new subthreshold leakage model is proposed in order to improve the static power estimation in general CMOS complex gates. Series-parallel transistor arrangements with more than two logic depth, as well as non-series-parallel off-switch networks are covered by such analytical modeling. The occurrence of on-switches in off-networks, also ignored by previous works, is considered in the proposed analysis. The model has been validated through electrical simulations, taking into account transistor sizing, operating temperature, supply voltage and threshold voltage variations.

The increasing complexity in particular of video and multimedia processing has lead to the need of developing the algorithms specification using software implementations that become in practice generic reference implementations. Mapping directly such software models in platforms made of processors and dedicated HW elements becomes harder and harder for the complexity of the models and for the large choice of possible partitioning options. This paper describes a new platform aiming at supporting the mapping of software specifications into mixed SW and HW implementations. The platform is supported by profiling capabilities specifically conceived to study data transfers between SW and HW modules. Such optimization capabilities can be used to achieve different objectives such as optimization of memory architectures or low power designs by the minimization of data transfers.

This work deals with the problem to optimise the energy consumption of an embedded system. On system level, tasks are assumed to have a certain CPU-usage they need for completion. Respecting their deadlines, slowing down the task system reduces the energy consumption. For periodically occurring tasks several works exists. But even if jitter comes into account the approaches do not suffice. The event stream model can handle this at an abstract level and the goal of this work is to present and solve the optimisation problem formulated with the event stream model. To reduce the complexity we introduce an approximation to the problem, that allows us a precision/performance trade-off.

A typical design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. The main goal of an estimation methodology, introduced in this paper, is to provide fast and accurate estimates of the instruction cache miss rate of data-intensive applications implemented on a programmable embedded platform with multi-level instruction cache memory hierarchy, during the early design phases. Information is extracted from both the high-level code description (C code) of the application and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. In order to automate the estimation procedure, a novel software tool named m-FICA implements the proposed methodology. The miss rate of two-level instruction cache can be estimated with high accuracy (>95%), comparing with simulation-based results while the required time cost is much smaller (orders of magnitude) than the simulation-based approaches.

Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.