Catálogo de publicaciones - libros

Settling time is one of the most important performance parameters for a whole class of amplifier, such as those employed in switched-capacitor-based circuits and analog-to-digital converters. In this work, analysis to predict and to minimize the settling time for amplifiers characterized by first-, second-, and third-order system-wise behaviour, is developed. The proposed method is very useful for design purposes. It allows amplifier poles to be placed directly in the complex plane, achieving the best-settled time response in accord with the desired accuracy level.

A low-voltage low power voltage reference realized in 0.35 CMOS technology will be presented. In order to achieve two important goals of low-power high performances bandgap references realized in the newer CMOS technologies – a low supply voltage and a small value of the temperature coefficient, a modified structure using dynamic MOS transistors (equivalent with a virtually lowering of the material bandgap) and a square-root curvature-correction will be implemented. The accuracy of the output voltage will be increased using an Offset Voltage Follower Block as voltage generator, with the advantage that matched resistors are replaced by matched transistors. The low-power operation of the circuit will be achieved by using exclusively subthreshold-operated MOS devices. Experimental results confirm the theoretical estimations, showing a minimum supply voltage of 2.5 and a temperature coefficient of about 9.4 / for an extended temperature range (173 <  < 423).

This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400× compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.

The increase of within-die variations and design margins is creating a need for statistical design methods. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts occurring during production. This method is first validated for 90nm and 65nm processes. Finally, this statistical timing analysis is applied on basic ring oscillators to evaluate the timing margins introduced at the design level by the traditional corner based approach.

The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern circuit designs may suffer from design uncertainties, unpredictable in the design phase or even after manufacturing. This paper presents an optimization technique to make pipeline circuits robust against delay variations and thus maximize timing yield. By trading larger flip-flops for smaller latches, the proposed approach can be used as a post-synthesis or post-layout optimization tool, allowing accurate timing information to be available. Experimental results show an average of 31% timing yield improvement for pipeline circuits. They suggest that our method is promising for high-speed designs and is capable of tolerating clock variations.

In this paper, we propose a gate-level NBTI delay degradation model, where the stress voltage variability due to PMOS transistors’ stacking effect is considered for the first time. Experimental results show that our gate-level NBTI delay degradation model results in a tighten upper bound for circuit performance analysis. The traditional circuit degradation analysis leads to on average 59.3% overestimation. The pin reordering technique can mitigate on average 6.4% performance degradation in our benchmark circuits.

To adress the problem of static power consumption, approaches as ABB and AVS have been proposed to reduce runtime leakage in integrated circuits. Applying these techniques is a trade off between power and delay, which is best decided early in the design flow. Therefore high level power and delay estimation is needed. In our work, we present a fast RT Level delay macro model considering supply and bias voltages and temperature. Errors below 5% combined with only few characterization data enables this approach to be used by high level design tools to support leakage optimization by e.g. and .

Design considerations for ultra low power circuits are presented through a study of circuit families operating at ultra low supply voltages. We examine static CMOS logic versus pass-transistor logic to determine which logic style is best suited for ultra-low power design. Furthermore, in this work we present a modification to Complementary Pass-gate Logic which improves its operation in ultra low power conditions. The operation of this modified CPL (MTCPL), in ultra low supply voltage conditions is compared to CMOS+, Dual Value Pass transistor Logic, and static CMOS in the same environment. The results show that although CMOS+ demonstrates the best energy delay characteristics for ultra low-power design, MTCPL yields the best energy at low data activities.

Practical and accurate Design-in Reliability methodology has been developed for designs on 90-45nm technology to quantitatively assess the degradation due to Hot Carrier and Negative Bias Temperature Instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology illustrating the capabilities of the methodology as well highlighting the impacts of the two degradations modes.

In modern digital ICs, the increasing demand for performance and throughput requires higher operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip clock signals with fast rise/fall times are among the most detrimental sources of electromagnetic (EM) noise, since not only they generate radiated emissions, but they also have a large impact con the conducted emissions, as the power rail noise localized in close proximity of the toggling clock edges propagates to the board through the power and ground pins. In this work, we analyze the impact of different clock distribution solutions on the spectral content of typical on-chip waveforms, in order to develop an effective methodology for EMC-aware clock-tree synthesis, which globally reduces the EM emissions. Our approach can be seamlessly integrated into a typical design flow, and its effectiveness is demonstrated with experimental results obtained from the clock distribution network of an industrial digital design.