Catálogo de publicaciones - libros

Crosstalk analysis has become an essential part of high performance design in nanometer technologies. Interconnects in nanometer technology have increased resistance and coupling capacitance due to process scaling. The crosstalk pulses are complex and require a new modeling approach. We show that current models such as triangular and Weibull exhibit as much as 31% error in propagated pulse for some crosstalk waves in nanometer technology. We present a methodology based on wave fitting as a model for crosstalk waves. We compare the accuracy of the wave fitting model proposed with existing wave models such as: Weibull, isosceles triangular and trapezoidal. We present the simulation results for different gates in 65nm Bulk CMOS technology and provide a comparison in error statistics for propagated crosstalk pulse. We demonstrate that our approach has a average propagated pulse error of less than 5% and improves the overall crosstalk analysis results by at least 67%.

A procedure called box-scan search which identifies possible weakness in a power distribution network of an LSI is proposed. In the procedure, node pairs having large voltage difference but located in close proximity are considered as good candidates for improving connections using additional wire. The virtual box is the grid space in which the node voltages are compared. Scans of node voltages of the virtual box generate a prioritized list of the fixing point candidate. Experimental results show effectiveness of the proposed procedure for pointing out the node pairs which requires low-impedance connection.

has shown to be a successful approach to bus temperature minimization. The idea at the basis of this technique is that of periodically permuting the routing of input bitstreams to the various bus lines, with the objective of temporally and spatially distributing the number of transitions over the entire bit-width, thus avoiding high switching activities to occur always on a few lines, which obviously causes an unnatural increase in temperature.

In this paper, we propose new encoding schemes which improve the capabilities of the approach of balancing the switching activities over the bus wires. The solutions we introduce are adaptive and dynamic in nature, as they select what bitstream goes to what bus line based on the actual bus traffic, thanks to some on-line monitoring capabilities which is offered by some ad-hoc hardware unit which runs in parallel at the transmitting and receiving ends of the bus.

The experimental results show that, on average, the proposed encoding schemes improve the transition balancing capabilities of the technique by a significant amount.

In this work, the necessity of combining signal encoding schemes with low-level anti-crosstalk techniques like spacing and shielding is analyzed. It is shown that in order to increase the throughput improvement and/or reduce the power consumption, coding schemes should be integrated with layout techniques since methods like spacing and shielding can be regarded as very simple encoding schemes. On this basis, a theoretical framework for assessing the improvement in throughput and/or power consumption is constructed. Furthermore, several possibilities to integrate coding with classical anti-crosstalk techniques are discussed.

Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEU) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at the sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory.

1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a non-linear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit, we prove that it is sufficient to consider a linear number of constraints. As an important preprocessing step we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100% to 200% while, on average, the power saving is simultaneously decreased by less than 7% to 12% respectively, compared to the optimal power saving with no error rate constraints.

The complexity of mobile devices is continuously growing due to the increasing requirements on performance. In portable systems such as smart cards, not only performance is an important attribute, but also the power and energy consumed by a given application. It is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. Both the optimization and the characterization are carried out mostly manually and are thus very time consuming processes. This paper presents an environment for automated instruction set characterization, based on physical power measurements. Further, an optimization system is presented that allows an automated reduction of power consumption based on a compiler optimization.

We present an accurate RT level estimation methodology describing the power consumption of a component under power gating. By developing separate models for the on- and off-state and the transition cost between them, we can limit errors to below 10% compared to SPICE. The models support several implementation styles of power gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate. We show, how the models can be integrated into a high level power estimation framework supporting design space exploration for several design for leakage methodologies.

Power is the number one constraint impacting today’s electronic designs. The need to minimize dynamic and static power consumption creates unique verification challenges. A common low power design technique involves switching off certain portions of the design (power islands) when that functionality is not required to reduce leakage power and restoring power when that functionality is needed again. This creates the need to save and restore state information with retention flops and latches, and to ensure the power island returns to a known good state when powered up.

Verification of correct design functionality of power islands within the context of a power management scheme has traditionally been performed at the gate level, if at all. Defect rectification at this level is costly in terms of resource and design cycle. This paper discusses the application of innovative techniques to enable power-aware verification at the RTL with traditional RTL design styles and reusable blocks.

Energy efficiency is a top requirement in embedded system design. Understanding the complex issue of software power consumption in early design phases is of extreme importance to make the right design decisions. Power simulators offer flexibility and allow a detailed view on the sources of power consumption. In this paper we present XEEMU, a fast, cycle-accurate simulator, which aims at the most accurate modeling of the XScale architecture possible. It has been validated using measurements on real hardware and shows a high accuracy for runtime, instantaneous power, and total energy consumption estimation. The average error is as low as 3.0% and 1.6% for runtime and energy consumption estimation, respectively.

The designer of an elliptic curve processor is faced with many design choices that include the algorithm and coordinate system to be used. The power consumption of elliptic curve processors is becoming increasingly important as such processors find new uses in power constrained environments. This paper studies the effect that algorithm and coordinate choices have on the power consumption and energy per point multiplication of an FPGA based, reconfigurable elliptic curve processor.