Catálogo de publicaciones - libros

In this work we consider coefficient reordering for low power realization of FIR filters on fixed-point multiply-accumulate (MAC) based architectures, such as DSP processors. Compared to previous work we consider the input data correlation in the ordering optimization. For this we model the input data using the dual bit type approach. Results show that compared with just optimizing the number of switches between coefficients, the proposed method works better when the input data is correlated, which can be assumed for most applications.

To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Float ing-gate MOS (FGMOS) is one of those techniques and has previously shown poten tially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transis tors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

This paper investigates the use of the Logarithmic Number System (LNS) as a low-power design technique for signal processing applications. In particular we focus on power reductions in implementations of FIR and IIR filters. It is shown that LNS requires a reduced word length compared to linear representations for cases of practical interest. Synthesis of circuits that perform basic arithmetic operations using a 0.18m 1.8V CMOS standard-cell library, reveal that power dissipation savings more than 60% in some cases are possible.

In systems-on-chip, allows energy savings. If only one global voltage is scaled down, the voltage cannot be lower than the voltage required by the most constrained functional unit to meet its timing constraints. allows better energy savings since each functional unit has its own independent clock and voltage, making the chip .

In this paper we propose a architecture, adapted to globally asynchronous and locally synchronous systems, based on a technique called . Compared to traditional power converters, the proposed is small and power-efficient, with no needs for large passives or costly technological options. This design has been validated in a STMicroelectronics CMOS 65nm low-power technology.

An evaluation of the fault tolerance which can be achieved by the use of time-redundancy techniques in integer multipliers has been conducted. The evaluated techniques are: swapped inputs, inverted reduction tree, a novel use of the half precision mode in a twin-precision multiplier, and a combination of the first two techniques. The faults which have been injected are single stuck-at-zero or stuck-at-one faults. Error detection coverage has been the evaluation criteria. Depending on the technique, the attained error detection coverage spans from 25% to 90%.

The quest for the universal memory has attracted many talented researchers and number of investors for years now. The objective is to develop a low cost, high-speed, low power, and reliable non-volatile memory. In practice, the universal memory system is more like an optimized combination of execution and storage memories, each of them having its own characteristics. Typically, execution memories manage temporary data and must be fast, with no endurance limitations. Different types of RAM memories are used to build an optimized hierarchy, including different levels of cache. In addition to RAM memories, non-volatile memories such as ROM or NOR flash used for code storage can be considered as execution memories when in place execution of the code is possible.

As process parameter dimensions continue to scale down, the gap between the designed layout and what is really manufactured on silicon is increasing. Due to the difficulty in process control in nanometer technologies, manufacturing-induced variations are growing both in number and as a percent of feature size and electrical parameters. Therefore, characterization and modeling of the underlying sources of variability, along with their correlations, is becoming more and more difficult and costly.

Digital power modelling is well developed today, through many years of active research. However analog power modelling lags behind. The aim of this paper is to discuss possible fundamentals of analog power modelling. Modelling is based on noise, precision, linearity, and process constraints. Simple elements as samplers, amplifiers and comparators are discussed. Analog-to-digital converters are used to compare predicted minimum power constraints with real circuits.

Mobile phones has already become far more than the traditional voice centric device. A large number of capabilities are being integrated into the higher-end phones competing with dedicated devices, including camera, camcorder, music player, positioning, mobile TV, and high-speed internet access. The huge volumes push the employment of the very latest silicon and packaging technologies, with respect taken to cost and high-volume production. While at one hand, the technology allows for integration of more features and higher performance, issues such as low hardware cost requirements, power dissipation, thermal issues, and handling the software complexity are increasingly challenging.

For wide bandwidth spectrometers there are several competing technologies to consider, digital, optical and various analog schemes. For applications demanding wide bandwidth and low power consumption in combination, autocorrelation based digital designs take advantage of Moores law and will take a dominating position in the coming years.