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The semiconductor industry has clearly moved into the era of nanoelectronics where the “the understanding and control of materials at the sub-100nm level” — the best established definition of nanotechnology [] — is essential to maintaining Moore’s Law. However nanoelectronics, like many other applications for nanotechnology, requires more than making single devices in small areas. To be commercially relevant, structures must be manufactured in volume and/or over large areas. And perhaps most fundamentally they must be produced at ever lower costs to drive adoption of new applications, grow end markets and provide the source of investment in next generation technology. In many instances, the invention of an appropriate manufacturing method may be of equal importance to the underlying device concept — there is perhaps no better example of than that of the IC itself where both Kilby (first realization) and Noyce (manufacturable process) are recognized as its primary inventors. We will define these methods of realization as “nanomanufacturing technologies” — i.e. the materials, process and measurement tools and technologies that deliver the required scale, cost, reproducibility and reliability to manufacture successful nanotechnology-based products.

We have developed an atomistic model for dopant diffusion in SiGe structures and we have implemented it in the kinetic Monte Carlo process simulator DADOS. The model takes into account (i) composition and stress effects on the diffusivity of interstitials, vacancies and dopants, (ii) SiGe interdiffusion, (iii) dopant segregation and (iv) the modifications of band-gap and charge levels. The model has been tested for B and Sb providing a very good agreement with available experimental data.

Possible arrangements of As in bulk Si have been investigated using ab initio calculations to establish the most stable configurations depending on As concentration and charge state. Consistently with these results we developed a continuous model for As activation and diffusion in Si. The model was implemented in the Sentaurus Process Simulator and calibrated using a wide range of experimental results available in the literature. It was independently tested for spike and flash annealing experiments with excellent results.

We have carried out molecular dynamics simulations of monatomic B and octadecaborane cluster implantations into Si in order to make a comparative study and determine the advantages and drawbacks of each approach when used to fabricate shallow junctions. We have obtained and analyzed the doping profiles and the amount and morphology of the damage produced within the target. Our simulation results indicate that the use of octadecaborane clusters for the implantation process shows several advantages with respect to monatomic B beams, mainly related to the reduction of channeling and the lower amount of residual damage at the end of range.

The optimal device structures and channel orientation for nanoscale strained-Ge heterostructure p-MOSFETs, are discussed through detailed Band-to-band-tunneling (including band structure and quantum effects), Low-field Mobility (k.p and Boltzmann Transport), Full-Band Monte-Carlo, and 1-D Poisson -Schrödinger Simulations. The tradeoffs between drive current (ION), intrinsic delay (τ), band-to-band-tunneling (BTBT) leakage and short channel effects (SCE) have been systematically compared in high mobility strained-Ge Heterostructure FETs (H-FETs).

Self-consistent full-band Monte Carlo (with multi-subbands) device simulations were performed to clarify the mechanism of drain-current enhancements for uniaxially strained bulk Ge-pMOSFETs with different channel/surface orientations. Unlike any conventional mobility studies, our device simulation enables us to probe fundamental roles of source-injection and channel backscattering in the practical bulk-MOSFET device structures with optimized channel/surface selections.

We have developed a system consisting of a full-3D process simulator for stress calculation and k · p band calculation that takes into account the subband structure. Our simulations are in good agreement with the experimental data of strained Si-pMOSFETs of 65nm technology devices. This system is a powerful tool to optimize device structures with all stress components.

A continuum model of phosphorus diffusion with germanium and carbon coimplant has been proposed and calibrated based on secondary ion mass spectroscopy (SIMS) profiles aiming at ultra shallow junction (USJ) formation in advanced CMOS technologies. The phosphorus diffusion behaviors are well captured by our model under various implant and annealing conditions, representing a significant step towards advanced n-type USJ formation technique using phosphorus and carbon coimplant for aggressively scaled CMOS technologies.

We use grain-focused models to study grain boundary (GB) migration (GBM) in polycrystalline Cu vias that interconnect MLM layers in 3D ICs. Curvature-driven GB velocities are calculated by PLENTE []–[] using the local mean curvature of the GBs, as described in Ref. 2. We use Comsol Multiphysics [] to calculate GB velocities due to thermally induced strain energy jumps across GBs []. The thermo-mechanical calculations needed for this are made using model structures that combine continuum models and grain-continuum (GC) models (see []–[], []); we call these ‘hybrid’ grain-continuum (HGC) models. Curvature driven GB dominates in this work; however, there are uncertainties in the absolute stress values used and how the relative magnitudes of these phenomena will change as the structure evolves.

As the design rule is scaled down, the electrical isolation of metal lines becomes critical. In a high density flash memory with 37nm (pitch=74nm) technology, the threshold voltage shift of ∼0.3V is found to be caused by tungsten micro-bridge between adjacent bit-lines. Simulations and experimental data showed that tungsten re-sputtering is occurred during the deposition of HDP (High Density Plasma)-SiO used as the filling dielectric between tungsten bit-lines. In this paper, the model for the tungsten re-sputtering is presented. The plasma simulations are performed to investigate the effects of process factors of HDP-SiO deposition on the formation of micro-bridge using in-house tool, PIE simulator.