Catálogo de publicaciones - libros

One of the major challenges in deep submicron semiconductor era is to control the increase of variations due to decreasing in feature size. Currently, Design for Manufacturing (DFM) method enables to optimize layouts reducing the influence of process variations on circuit []. In this paper, we investigated the process margin analysis methods which are related to process defects of high aspect ratio (HAR) contact and short failures between lines. From this methodology, yield limiting process failures are identified and nano-scale defects in cells are virtually monitored without destructive method. This novel simulation methodology makes it possible to estimate the number of void defects of floating gate in Flash memory and predict Breakdown Voltage (BV) of the capacitor in DRAM. As a result, the defect level which is related yield has been decreased from 42% to 2.1% in 60nm Flash device and BV of capacitor has been virtually monitored in 80nm DRAM device.

We have developed a topography simulation method which combines advanced level set techniques for surface evolution with Monte Carlo flux calculation. The result is an algorithm with an overall complexity and storage requirement scaling like (log) with surface disretization. The calculation of particle trajectories is highly optimized, since spatial partitioning is used to accelerate ray tracing. The method is demonstrated on Si etching in SF/O plasma.

Process induced stress is one of the key performance boosters to qualify advanced MOSFET technological node. 3D Finite Element simulation (FEM) is carried out to accurately model Contact Etch-Stop Layer (CESL) stress-related layout effects. Indeed, the corresponding stress field in transistors greatly depends on many parameters. Correlations with electrical measurements demonstrate results relevance. In addition to the effect of the transistor size, the environmental features of the MOSFET, such as the density of adjacent structures including dummy and Al-contact play a major role. As a result, differences in layout lead to considerably change the stress-induced transistor performance.

We proposed a simple model to simulate topography and composition of deposited films. Our model described topography and composition of deposited fluorocarbon films in CF/CO/O/Ar plasma etching. Analysis of compositions facilitated making of the reactor and surface models, and our model could treat the gas flow and open width dependency of the SiO etching. It was very useful in designing devices for easy manufacturing.

We present calculations for the transport properties of single molecules and carbon nanotubes (CNT) bridged between electrodes. Here we use two calculation methods. One is the recursion-transfer-matrix (RTM) method, which is a reliable tool to calculate accurate scattering waves in plane-wave expansions. Combined with the NEGF method and density-functional formalism, we perform calculations of transport properties through single molecules. The other is the time-dependent wave-packet approach. Based on the linear-response Kubo formula, we perform O(N) calculation for the transport of large systems. We apply the method for the CNT-FET device and find that the control of the contact to electrodes are crusial for the device performance.

In MEMS fabrication micro-mechanical components have to be partially released from a substrate. Selectively etching away sacrificial layers, such that a free standing structure remains, is a widely used technique for this purpose. Free standing structures allow MEMS devices to induce or to sense mechanical movements or vibrations.

During sacrificial etching lower etch rates than the blanket ones are observed. This reduction can be explained by additional factors like the transport of the etch medium and its etch reactants via the relatively narrow (in relation to the etch depth) already etched channel under the free standing structure.

Sacrificial etching is mainly controlled by process parameters like the etch agent concentration, chamber temperature, and pressure. Furthermore, local geometrical features and the nature of chemical reactions are responsible for different etch speeds at material boundaries and, therefore, they influence the propagation of the etch front. In order to analyze these effects we have developed a three-dimensional topography simulation tool and the required models for the etch rates.

This paper describes our ab initio method to evaluate the effective work function of a MOS metal gate on HfO oxide which is different from the vacuum one because of the Fermi pinning. The computation relies on Density Functional Theory (DFT) and Many Body theory. Firstly a monoclinic cell is computed using DFT to obtain a band structure; this one is corrected using the GW approximation. Then a stack made of W + HfO is computed and using Van de Walle and Martins method, the energy bands alignment along the stack is obtained. Finally HfO energies in the stack are corrected according to our previous computation on the HfO cell. This calculation brings an evaluation of the valence band offset at the W/HfO interface and the effective work function of W on HfO.

In this paper, we present our study on energy configurations, minimum energy path (MEP), and migration energy for neutral indium diffusion in a uniaxial tensile strained {100} silicon layer. Our calculation of the electronic structure allowed us to figure out transient atomistic configurations during the indium diffusion in strained silicon. We found that the lowest-energy structure (Ins - Si) consists of indium sitting on a substitutional site while stabilizing a silicon self-interstitial in a nearby tetrahedral position. Our calculation implied that the next lowest energy structure is In, the interstitial indium at the tetrahedral position. We employed the nudged elastic band (NEB) method for estimating the MEP between the two structures. The NEB method allowed us to find that that diffusion pathway of neutral indium is kept unchanged in strained silicon while the migration energy of indium fluctuates in strained silicon.

A new deterministic approach to the electronic noise calculation based on the non-equilibrium Green’s function formalism with the electron-phonon scattering mechanisms is presented for nanoscale devices, and the diffusion noise phenomena at zero frequency are investigated. Our approach can handle the quantum effects naturally and it gives physical insight about the noise in nanoscale devices. As an application, silicon nanowire field effect transistor is considered and the numerical results show that the Johnson-Nyquist theorem is satisfied at equilibrium and the excess noise occurs in the presence of current transport.

A perturbation technique is developed for the analysis of random doping induced fluctuations (RDF) of small-signal equivalent circuit parameters in semiconductor devices. This technique is based on the computation of the doping sensitivity functions of parameters of interest by using the admittance matrix parameters and is applied to the study of RDF of equivalent circuit parameters in a 40-nm channel length MOSFET. The presented technique can be easily extended to the analysis of RDF in other semiconductor devices such as SOI, HEMT, etc.