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This paper describes the hot-carrier (HC) behaviour of a high-voltage 0.35 µm n-channel lateral DMOS transistor (LDMOSFET). Self-heating effects during HC stress have to be taken into account for the HC stress analysis. Peak I and I degradations were observed at the stress bias V = 0.8 V and V = 2.5 ∼ 3.0 V, respectively. Together with TCAD simulations and measurements, one can clearly explain the HC effects occurring near the bird’s beak region and show their impact on the I and I degradations.

A master equation model is developed for dark injection from a metallic electrode into a random hopping system, representing a conjugated polymer or a molecularly doped polymer. A master equation allows for the inclusion of the image force effect on the charge injection process and for a separate analysis of the forward hopping and back-flow components. This model yields the injection current as a function of electric field, temperature, energy barrier between metal and organic layer, and energetic width of the distribution of hopping sites. Good agreement with experimental data is found.

In this work, the RF performance of Si nanowire transistors (SNWTs) is computationally investigated, including RF figures of merit, impacts of parasitic effects and nanowire cross-sectional shape fluctuation caused by process variation. The simulated results show superior RF scalability of SNWTs and severe impacts of parasitic capacitance and process fluctuations. The influence of gradient doping profile in source/drain extension region of SNWTs on RF application is also studied.

In this work we present a study of the combined effects of the variation of process parameters and geometry in a 65 nm technology through consistent three-dimensional TCAD process and device simulations. Channel lengths and widths together with two critical process parameters obtained through a screening experiment are examined in a 3-level full-factorial design of experiments. The results show an increased impact of process variations for short and narrow structures.

A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (np) polysilicon gates. CMOS-compatible V’s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

We present a statistical methodology for leakage power estimation, due to subthreshold and gate tunneling leakage, in the presence of process variations, for 65 nm CMOS. The circuit leakage power variations is analyzed by Monte Carlo (MC) simulations, by characterizing NAND gate library. A statistical “hybrid model” is proposed, to extend this methodology to a generic library. We demonstrate that hybrid model based statistical design results in up to 95% improvement in the prediction of worst to best corner leakage spread, with an error of less than 0.5%, with respect to worst case design.

As CMOS technology is advanced in recent years, the operation of SRAM becomes critical issue for further scaling. It is crucial for realizing the SRAM to keep static noise margin (SNM) and write margin (WM) large enough to get stability and overcome random dopant and process fluctuations. Also, suppression of leakage current is another key issue. The major sources of leakage current are the gate direct tunneling current, the sub-threshold leakage and the reverse biased band-to-band-tunneling junction leakage. To reduce total chip power, these leakage components must be suppressed.

In this paper, we have focused on the optimization of low power operation SRAM circuit for 32 nm node with TCAD optimizing the relationship among margin, leakage current and access time. To conduct the circuit design principle, we define the new quality factor and evaluate the 32nm SRAM performance with this defined formula.

Full 3D numerical process and device simulations have been performed in order to optimize device design of multigate FETs (MuGFETs) and the underlying fabrication processes. At first process simulation parameters have been calibrated to measurement data of pre-development process results. Based on this, device electrical performance has been assessed for different gate length, fin doping, implant conditions, fin height, fin width, gate oxide and box thickness by means of typical device parameters.

A comprehensive technique for the accurate extraction of the effective lateral doping abruptness and the spreading resistance components is applied to both Si (100) and Si (110) MOSFETs. The spreading resistance components under extension-to-gate overlap and spacer regions are successfully correlated to the lateral extension (EXT) doping abruptness by the relationship between on-resistance (R) and overlap capacitance response (C). The lateral doping profile difference is extracted between (100) and (110) PMOS, which successfully explains higher external resistance in measured (110) PMOS.

To clarify the microscopic mechanism of Negative-Bias Temperature Instability (NBTI), which is one of serious reliability issues in CMOS technology, the transfer reaction of the positive fixed charge at the Si/SiO interface accompanied by hydrogen migration was investigated using the ab initio molecular orbital method. Comparing the activation energies, we determined the most likely reaction path. We found that the reaction path can be stabilized more by migration of an electrically neutral H atom from a Si substrate to a positively charged O atom than by migration of a proton from a Si substrate to an electrically neutral O atom. The calculated Mulliken atomic charges and atomic spin densities also supported our conclusion.