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Numerical device simulations show that slight extensions of the p-emitter thickness in 4H-SiC high voltage blocking bipolar pin diodes lead to a signi cant lowering of the forward voltage drop under high injection conditions at room temperature. The advantage of higher recombination currents in the enlarged p-region resulting from an enhanced excess carrier density overbalances the higher series resistance of the high-doped p-region. Both effects have their origin in the incomplete ionization of the acceptor dopants in the p-emitter. Hence, they become less signi cant at higher temperatures. A temperature dependent optimal p-emitter thickness is identi ed.

IGBT device destruction often occurs localized at the edge termination. Among various termination techniques, “variation of lateral doping” (VLD) is a promising candidate to increase the ruggedness of IGBT chips. We analyzed the time-dependent behavior of VLD edge termination during avalanche breakdown by numerical simulations demonstrating the advantage of this technique. Measurements on IGBT test devices with VLD edge termination are in agreement with the simulations.

Role of scattering has been discussed as scattering still controls drain current of decananometer MOSFET’s, including the number of scattering events per unit length or gate length. Nevertheless, as scattering mechanisms have various angular dependences, in this paper, meanings of ‘number’ of scattering events are discussed and ‘effective’ scattering number is introduced to interpret quasi-ballistic transport. This concept is shown to be useful to understand the quasi ballistic transport and the role of various scattering mechanisms especially when back-scattering is not negligible.

We present a parameter extraction technique for higher-order transport models for a 2D electron gas in ultra thin body SOI MOSFETs. To describe 2D carrier transport we have developed a self consistent Schrödinger-Poisson Subband Monte Carlo simulator. The method takes into account quantization effects and a non equilibrium distribution function of the carrier gas, which allows an accurate description of the parameter behavior for high electric fields. Finally the results are compared with the transport parameters of 3D bulk electrons and the influence of the channel thickness on the mobility is investigated.

A robust algorithm to get the chemical potential of the particle reservoirs for the self consistent full 2D Schrödinger-Poisson solver is proposed. Using this algorithm we study the effect of junction depth on ballistic current. Simulation results show that shallow junctions come with much better on to off current ratio while it keeps the on-state transconductance at the same level as the deeper junction device.

We have extensively investigated transport properties of nanowire MOSFETs and single-electron/single-hole transistors by experiments and band calculations. Special focus has been placed on measurements and physics of the channel direction dependence and charge polarity dependence. We adopted a special device structure with a common n-type and p-type channel. We confirmed that a [110]-directed nanowire p-type FET has the smallest fluctuations caused by the size variations. We also verified that a [100]-directed single-hole transistor is the best device for the single-charge transistor operations. Actually, we observed Coulomb blockade oscillations with the record high peak-to-valley-current ratio of 480 at room temperature in a [100] single-hole transistor.

As device sizes shrink towards the nanoscale, CMOS development investigates alternative structures and devices. Existing CMOS devices will evolve from planar to 3D non-planar devices at nanometer sizes. These devices will operate under strong confinement and strain, regimes where atomistic effects are important. This work investigates atomistic effects in the transport properties of nanowire devices by using a nearest-neighbor tight binding model (sps*d-SO) for electronic structure calculation, coupled to a 2D Poisson solver for electrostatics. This approach will be deployed on nanoHUB.org as an enhancement of the existing Bandstructure Lab.

Source-to-drain tunneling is investigated for Si triple-gate nanowire transistors. The full-band quantum transport problem is solved in an atomistic basis using the nearestneighbor tight-binding method. It is self-consistently coupled to the threedimensional calculation of the electrostatic potential in the device using the finite element method. This procedure is applied to the computation of — transfer characteristics of transistors with different channel orientations such as [100], [110], [111], and [112] for gate lengths ranging from 4 nm to 13 nm. The subthreshold swing is then extracted from the results to determine the scaling limit of nanowire transistors.

We report on Terahertz (THz) current oscillations in single-walled semiconducting zig-zag carbon nanotubes (CNTs) upon application of a step DC bias, as shown in Fig. 1. To investigate the electron transport on a tube with fundamental indices of = 13 and = 0, we developed a transient ensemble CNT Monte Carlo (MC) simulator. In the simulator, electron transport in time and space is resolved with the effects of charge distribution on the potential profile along the tube. The solution shows that electron-phonon resonances give rise to current, velocity and concentration oscillations upon application of a DC bias.

Atomistic hole transport simulation based on a nonequilibrium Green’s function method and a tight-binding approximation has been performed for two types of ultrathin double-gate silicon-on-insulator MOSFETs; (i) <100>-device on a {100} substrate where the current flows along the <100> direction and (ii) <110>-device on a {110} substrate where the current flow direction is the <110> direction. Simulation results show that the difference in crystalline orientation of the devices greatly affects ballistic hole current due to a strong confinement-induced mixing of heavy- and light-hole states.