Catálogo de publicaciones - libros

A methodology for mesh generation with nodes placed on the atomic positions of the structure is presented. The meshing strategy is based on the use of patterns to decompose a unit cell of the target crystal into tetrahedra. The mesh generation procedure has been applied to crystalline Si and SiO (α-quartz) as well as to their interface. The constructed meshes have been consequently randomly populated by dopants using Monte Carlo approach. The dopants are replacing silicon atom in nodes of the crystal. The ‘atomistic’ mesh populated with random discrete dopants has been used to simulate an ensemble of microscopically different double gate MOSFETs in order to demonstrate the functionality of the meshing methodology.

The influence of line edge and gate interface roughness on SOI-MOSFET performance is studied by simulation. Both types of roughness were implemented in the device simulator SIMBA through the Fourier synthesis approach and the simulations were performed with the drift diffusion and the quantum drift diffusion models. Scaled transistors showed more sensitivity to rough interfaces with shallow junctions.

Numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along <110> in terms of the device performance of strained 65nm-node nMOSFETs with Contact Etch Stop Layer (CESL), and that both the shear strain component and the quantum confinement effect play an important role in this superiority.

A novel stress enhancement effect based on the damascene gate process with embedded SiGe (eSiGe) S/D for pFET is analyzed in detail, using stress simulation and Ion measurement, for the first time. Removal of a dummy poly-Si gate eliminates the repulsive force from the gate with a resulting enhancement of lateral compressive stress from eSiGe S/D. The stress enhancement effect is proved by device fabrication and measurement. Furthermore, a new channel recess process is proposed and investigated. Channel recess further increases stress at the channel. This effect is also confirmed by measurement, resulting in 14% current enhancement.

Stressed etch stop liners (ESL) are a common way to increase device performance. Here we investigate the layout dependent channel stress for mono- and multi-layer deposition. By means of empirical pseudopotential method full band structures are calculated and based on full band Boltzmann equation mobilities are extracted. We present for the first time nonlinear mobility enhancement maps for two strain components, in channel out-of-plane direction, showing that for typical ESL conditions both strain components are important for NFET and PFET.

Three-dimensional (3D) stress, process and device simulation is performed for nMOS-FETs with widths from 0.5 µm to 0.1 µm and gate lengths from 100 nm to 45 nm. Stress originates from a cap-liner with 2 GPa tensile stress. Drift-diffusion simulation with the linear piezoresistance model is employed considering either the position-dependence of stress or using a constant stress tensor obtained from averaging the stress in the source-side of the channel over a cuboid extending over the full device width.

Considering a space-dependent or a constant stress tensor turns out to yield almost the same linear and saturation current enhancements. This permits to use the constant stress obtained from 3D stress simulation for much faster 2D process and device simulation. In particular, also only one band structure is needed for Monte Carlo device simulation.

The two-step recessed SiGe Source/Drain (S/D) structure, which is one of the embedded SiGe S/D engineering techniques, is a leading candidate for advanced pMOSFETs from the viewpoint of good roll-off characteristics and high channel strain. In this paper, we reveal the merits of this technology for the application to the 32 nm technology node, including the methodology for suppressing the layout effect by TCAD analysis.

In this work, we investigate multiple FIN FinFET source/drain designs to reduce series resistance and source/drain-to-gate capacitance. The tradeoffs between the increased parasitic capacitance and reduced parasitic resistance are explored using 3D device simulations.

This paper reports a novel L-shaped Impact-ionization MOS (LI-MOS) transistor structure that achieves a subthreshold swing of well below 60 mV/decade at room temperature and operates at a low supply voltage. The device features an L-shaped or elevated Impact-ionization region (I-region) which displaces the hot carrier activity away from the gate dielectric region to improve hot carrier reliability and stability problems. Device physics and design principles for the LI-MOS transistor are detailed through extensive two-dimensional device simulations. The LI-MOS transistor exhibits excellent scalability, making it suitable for augmenting the performance of standard CMOS transistors in future technology generations.

We developed a new prototype TCAD tool for wafer processing, particularly to predict BMD(bulk micro defects) distribution, metal gettering characteristics, stress/slip behaviors from the view points of industry such as device reliability and reproducibility. We present herein (i)system concepts and basic models of the tool, (ii)notable output results of BMD radius/profiles in terms of initial interstitial oxygen ([O]) concentration and process sequences in conjunction with metal gettering and typical stress/slip behaviors. We also discuss thermal budget customization with emphasis on substrate stiffness and gettering efficiency for reliability and reproducibility improvements in scaled devices.