Catálogo de publicaciones - libros

Mobile gaming is playing an important role in the entertainment industry. Good performance is a critical requirement for mobile games in order to achieve acceptable running speed although mobile devices are limited by scarce resources. Object-oriented programming is the prevalent programming paradigm and this is true for mobile game development as well. As the origin of object-orientation (OO) is not targeting the embedded software domain, there is suspicion as to OO’s usability for embedded software, especially with respect to mobile games. Questions arise like how OO and to what degree OO will affect the performance, executable file size, and how optimization strategies can improve the qualities of mobile game software. In this paper we investigate these questions within the mobile Role-Playing-Game (RPG) domain using five industrial mobile games developed with OO. We re-implemented these five RPGs with a structural programming style, by reducing the inheritance relationships, removing excessive classes and interfaces. Some additional optimizations are also applied during the re-implementation, such as the tackling of performance bottleneck methods, using more efficient algorithms. New games after optimizations run on average almost 25% faster than the corresponding original games, with a maximum of 34.62% improvement; the memory usage is decreased by more than 10% on average and 17.56% as a maximum; we also achieved a 59% code reduction and a 71% Jar file decrease after optimization. Therefore if developers are aiming for mobile game performance, we conclude that they should use as few OO features as possible. Structural programming can be a very competitive alternative.

Hard disks, most prevalent mass-storage devices, have high power consumption and high response time for random I/O requests. Recent remarkable technology improvement of flash memory has made it a rising secondary storage device but flash memory still has high cost per bit. Usage of heterogeneous storage devices such as a pair of a hard disk and a flash memory can provide reasonable cost, relatively acceptable response time, and low-power consumption. In this paper, we propose a novel buffer cache replacement algorithm which targets a mobile computing system with a heterogeneous storage pair of a hard disk and a flash memory. The algorithm partitions the cache per each device and adjusts the size of each partition based on the performance indices of the devices, and manages each partition according to workload patterns. Simulations show that the proposed algorithm yields a hit rate up to two times higher than LRU on the typical mobile traces according to the cache size and achieves also better system I/O response time and energy consumption.

This paper proposes a lightweight runtime engine that is the core part of the wireless Internet platform of mobiles devices such as cellular phones or PDAs. The proposed lightweight runtime engine downloads and executes mobile applications in the binary form. Its memory footprint is less than 100 Kbytes and consists of the lightweight scheduler module, memory management module, dynamic reconfiguration module, event handler module, and timer module. The lightweight scheduler can process events 13% faster than a competitive technique which is the widely used thread-based scheduler. The memory management module works 6 ~10 times faster than other memory management algorithms, and the proposed dynamic reconfiguration module also shows a good performance in reconfiguring the platform software.

As an important application domain of embedded software, auto-motive software is playing a more important role within automotive industry. There are some essential issues to be resolved; managing software complexity, reducing software cost, and shortening time-to-market. An effective solution to these issues is to reuse generic Electronic Control Units (ECUs) in building various ECUs rather than building every piece from scratch. Generic ECU is an ECU level reuse unit which consists of automotive components and embeds variability. Among the reuse approaches, Product Line Engineering (PLE) can be effectively applied in developing generic ECUs. However, current PLE methodologies do not effectively support developing generic ECUs. Hence, in this paper, we first define a meta-model of generic ECUs. Then, we define variability types and variation points for generic ECUs. Based on the meta-model and variability types, we propose a product line process for developing ECUs. To assess the applicability of the proposed meta-model and the PLE process, we present the case study of developing an automotive ECU for Window Control System (WCS).

One of the key functionality of embedded-computer systems is control and data exchange among its building modules. Different size terminal sensors, microprocessor sub-systems, specialized devices, etc. should be able to smoothly exchange data and control notifications. This is often a difficult and time consuming task for a designer, mostly due to diversity of components. Usually the protocols and their realizations have to be implemented separately for each specific case. Therefore it would be desirable to have a definition of a protocol for data exchange and control that fits a certain class of such systems. In this paper we propose a solution to this problem which can be easily applied to different computer platforms. We start with the definition of the proposed DXC protocol. Then we present its object-oriented implementation. This way our proposition can be re-used on different platforms. The presented solution was employed with success to the suite of embedded systems for communication measurements and showed robustness and flexibility.

The paper presents a novel mapping and routing technique for the mesh based NoC design problem with an objective of minimizing the energy consumption and normalized worst link-load. The proposed algorithm is a particle swarm optimization (PSO) based two phases process, one is mapping core onto NoC, and another is the allocation of routing path. The proposed algorithm uses a novel representation for PSO particle. Experimental results show that the proposed technique can reduce the normalized worst link-load by 20% on average while guarantee a low energy consumption.

On-chip trace data contains run-time information of embedded multi-core processors for software debug. Trace data are transferred through special data path and output pins. Scheduling for combining the traffic of multi-source trace data is one of key issues that affect performance of the on-chip trace system. By analyzing features of trace traffic combination, a lazy scheduling algorithm based on the service threshold and the minimum service granularity is proposed. The queue length distribution is constrained by configurable service threshold of each queue, and switching overheads are reduced by lazy scheduling and configurable minimum service granularity. Two metrics of buffer utilizations on overflowing are presented to evaluate the efficacy of queue priority assignment. Simulation results show that the algorithm controls the overflow rate of each queue effectively and utilizes the buffer capacity according to the queues priority assigned sufficiently. The algorithm is realized in Verilog-HDL. Comparing with a leading method, the overflow rate is reduced 30% with additional 2,015um^2 in area.

Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimization technique has been given more attention, on-chip instruction memory optimization should not be neglected. We propose in this paper some algorithms for a memory offset assignment for embedded DSP processors in order to minimize the number of instructions for address register operations. Extensive experimental results demonstrate the efficacy of our solution.

With the development of network storage technology, some massive storage system architectures have exposed some drawbacks. How to remove the server bottleneck and decrease the loss rate of I/O requests have become an issue of increasing importance in the designing of network storage systems. In this paper, object-based storage system (OBSS) and RAID-based object storage device (RAID-based OSD) are briefly presented. Based on RAID-based OSD, an object subsection storage policy for the hot object files is put forward to increase the acceptance rate of I/O requests and improve the I/O performance of OBSS. Analytical and experimental results show that it is reasonable and effective.

In a sensor network, exploiting the correlation among different sources allows a significant reduction of the transmitted energy at the cost of a complex decoder scheme. This paper introduces the first hardware implementation for joint source-channel decoding of correlated sources. Specifically, a dual-clustered VLIW processor with a highly optimized datapath is presented.