Catálogo de publicaciones - libros

The recent advance of L4 microkernel technology enables building a secure embedded system with comparable performance to a traditional monolithic kernel-based system. According to the different system software architecture, the execution behavior of an application in microkernel environment differs greatly from that in traditional monolithic environment. Therefore, we need a performance profiler to improve performance of the application in microkernel environment. Currently, L4’s profiling tools provides only program-level information such as the number of function calls, IPCs, context switches, etc. In this paper, we present L4oprof, a system-wide statistical profiler in L4 microkernel environment. L4oprof leverages the hardware performance counters of PMU on a CPU to enable profiling of a wide variety of hardware events such as clock cycles and cache and TLB misses. Our evaluation shows that L4oprof incurs 0~3% higher overhead than Linux OProfile. Moreover, the main cause of performance loss in L4Linux applications is shown compared with Linux applications.

Recent research on embedded real-time systems has focused on dynamic power management for fault-tolerance or dependability. In this paper, we provide an adaptive checkpointing scheme for fixed priority-based DVS scheduling in dependable real-time systems. Since there are some trade-offs in selection of dynamic processor scaling in terms of energy consumption and task reliability, we provide an adaptive energy-aware scaling assignment scheme with the feasibility test for fixed-priority scheduling with checkpointing. In the provided scheme, we analyze the number of tolerable faults of a task and the optimal checkpointing interval in order to meet the deadline and guarantee its specified reliability. The feasibility analysis of the fixed priority-based scheduling algorithm in dependable real-time systems is provided as well.

With the rapid development of embedded systems, battery life becomes a critical restriction factor. Dynamic voltage scaling (DVS) has been proven to be an effective method for reducing energy consumption of processors. This paper proposes an energy-saving algorithm under a task model (the MSPR model) where a task consists of multiple subtasks with different fixed priorities. This algorithm includes two parts. The first part is a static algorithm, which exploits the relationship among tasks to set the slowdown factors of subtasks. The second part is an algorithm that dynamically reclaims and reuses the slack time of precedent subtasks during the execution of tasks. To the best of our knowledge, this is the first work for energy-efficient scheduling under the complex periodic real-time task model where a task consists of multiple subtasks with different fixed priorities. Experimental results show this method can reduce energy consumption by 20%-80%, while guaranteeing the real-time requirements of systems.

In recent years we have seen an increase in the complexity of embedded system design and in the difficulties of their verification. As a result, engineers have been trying to verify the specifications at a higher level of abstraction. In this paper we present an automated tool which is able to perform runtime verification of a programs logical properties asserted by the programmer. The idea is to leverage the Assertion Based Verification language PSL, which is widely used by hardware engineers, extending it to the software verification of C language programs. The properties expressed in a simple subset of PSL are evaluated by the tool during full system simulation. Like in hardware Assertion Based Verification, the tool can handle both safety properties (absence of bad events) and liveness properties (good events eventually happen). The liveness property is not widely supported in existing verification tools.

For a fault tree, especially for a dynamic fault tree, the occurrence of top event depends on not only the combination of basic events, but also on the occurrence order of basic events. Cut sequence is a set of basic events that fail in a particular order that can induce top event. Cut sequence set (CSS) is the aggregate of all cut sequences in a fault tree. The paper puts forward an algorithm, named CSSA (CSS Algorithm), to generate the CSS of a fault tree. CSSA uses sequential failure symbol (SFS) to describe the sequential failure relationship between two events. And then, cut sequence can be expressed by sequential failure expression (SFE), which is a chain of basic events connected by SFSs. In order to get the CSS, SFS transformation is applied to static gates and dynamic gates, the result of which is reconstructed to the standard form of CSS according to the inference rules of SFE. At length, an example is used to illustrate the detailed processes of the approach. CSSA provides a new qualitative method that extends the existing fault tree analysis models.

Pattern matching is one of the most performance critical components in network intrusion detection and prevention system, which needs to be accelerated by carefully designed architectures. In this paper, we present a highly parameterized multilevel pattern matching architecture (MPM), which is implemented on FPGA by exploiting redundant resources among patterns for less chip area. In practice, MPM can be partitioned to several pipelines for high frequency. This paper also presents a pattern set compiler that can generate RTL codes of MPM with the given pattern set and predefined parameters. One MPM architecture is generated by our compiler based on Snort rules on Xilinx FPGA. The results show that MPM can achieve 4.3Gbps throughput with only 0.22 slices per character, about one half chip area than the most area-efficient architecture in literature. MPM can be parameterized potential for more than 100 Gbps throughput.

In this paper, a fault-tolerant control method is presented with an application to steer-by-wire (SBW) system. SBW is a network-based vehicle steering system in which the mechanical linkage and hydraulics are replaced by electrical motors and fieldbus networks. Since failure of a steering system may result in a catastrophic accident, SBW can be considered as a safety-critical embedded system for which very high level of dependability must be satisfied. This paper proposes an effective control strategy to tolerate faulty actuators. The proposed method has a simple structure to be implemented on low cost embedded processors. The reconfiguration strategy consists of two fold: i) a smart actuator of which embedded microprocessor provides the fast and accurate diagnostic information through a time-triggered fieldbus, and ii) an IMC-PID controller which is capable of tolerating the effect of faults based on the diagnostic information being sent from the smart actuator. Simulation results with a SBW model show that the proposed method can enhance the system dependability in the presence of faults without using any redundant actuators.

Confidentiality, integrity, and authentication services are critical to preventing an adversary from compromising the security of a Wireless Sensor Network (WSN). An essential component of any key-based security solution is managing the encryption keys to providing this protection. Hence, we propose a novel group key management scheme based on the key-chain tree mechanism for the clustered WSNs in this paper. In this scheme, the functions of key management are decoupled and distributed among multiple network elements of the clustered WSNs for providing compromise/failure resistance. This scheme also supports rekeying to enhance network security and survivability against the node capture. Analysis results show that the scheme does provide a secure encryption of the messages even if the revoked sensor nodes collude with each other or the cluster head is compromised.

Unlike Internet design policies of early stage, various types of tunneling are currently used in Internet for IPv4/IPv6 transition, IP multicasting and IP mobility. As tunneled packets have dual IP headers, general firewall systems apply the filtering rules only to the outer header but not to the inner header when these packets pass the firewall. Thus, many present firewall systems may have serious security problems to packet filtering for tunneled packets. To resolve this issue, a new packet filtering mechanism to filter tunneled packets is proposed in this paper. We design and implement the packet filtering mechanism by using Linux Netfilter. Through this study, the packet filtering system was also found operating correctly in the IPv6-in-IPv4/IP-in-IP tunneling.

This paper focuses on calculating an end-to-end packet delay optimization for Quality of Service (QoS) in a mobile ad hoc network (MANET). Each intermediate node in an active path can achieve the optimized data rate which is obtained by using Lagrangian function and the end-to-end packet delay constraint. It is shown that the amount of data rate compared to the one which is not optimized can be saved in the proposed algorithm.