Catálogo de publicaciones - libros

Simplified fuzzy ARTMAP(SFAM) is a simplification of fuzzy ARTMAP(FAM) in reducing architectural redundancy and computational overhead. The performance of individual SFAM depends on the ordering of training sample presentation. A multiple classifier combination scheme is proposed in order to overcome the problem. The sum rule voting algorithm combines the results from several SFAM’s and generates reliable and accurate recognition conclusion. A confidence vector is assigned to each SFAM. The confidence element value can be dynamically adjusted according to the historical achievements. Experiments of recognizing mechanical workpieces have been conducted to verify the proposed method. The experimental results have shown that the fusion approach can achieve reliable recognition.

In this paper, we investigate fuzzy bidirectional associative memory (BAM) neural networks with finite distributed delays. Easily verifiable sufficient conditions for global exponential periodicity of fuzzy BAM neural networks with finite distributed delays are obtained.

In this paper, we propose design methodology of optimized Information granulation based genetically optimized Hybrid Self-Organizing Fuzzy Polynomial Neural Networks (IG_gHSOFPNN) by evolutionary optimization. The augmented IG_gHSOFPNN results in a structurally optimized structure and comes with a higher level of flexibility in comparison to the one we encounter in the conventional HSOFPNN. The GA-based design procedure being applied at each layer of IG_gHSOFPNN leads to the selection of preferred nodes (FPNs or PNs) available within the HSOFPNN. The obtained results demonstrate superiority of the proposed networks over the existing fuzzy and neural models.

This paper outlines all the computational methods which have been applied to the conflict management. A survey of all the pertinent literature relating to conflict management is also presented. The paper then introduces the Takagi-Sugeno fuzzy model for the analysis of interstate conflict. It is found that using interstate variables as inputs, the Takagi-Sugeno fuzzy model is able to forecast conflict cases with an accuracy of 80.36%. Furthermore, it found that the fuzzy model offers high levels of transparency in the form of fuzzy rules. It is then shown how these rules can be translated in order to validate the fuzzy model. The Takagi-Sugeno model is found to be suitable for interstate modeling as it demonstrates good forecasting ability while offering a transparent interpretation of the modeled rules.

The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI design. In addition, artificial neural network based on FPGAs has fairly achieved with classification application. The programmability of reconfigurable FPGAs yields the availability of fast special purpose hardware for wide applications. Its programmability could set the conditions to explore new neural network algorithms and problems of a scale that would not be feasible with conventional processor. The goal of this work is to realize the hardware implementation of neural network using FPGAs. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL) and is implemented in FPGA chip. The design was tested on a FPGA demo board.

The hardware random number generator is a source of unpredictable, statistically random stream sequences. Critical cryptography applications require the production of an unpredictable and unbiased stream of binary data derived from a fundamental noise mechanism. In this paper, we analyzed hardware random number generator with Gaussian noise using randomized algorithm in respect of security consideration. In this paper, hardware random number system on embedded Linux on chip (LOC) processor, MC68328, is reviewed to reduce the statistical property of the biased bit stream in the output of a random number generator. In experiments of the randomness evaluation for the randomized algorithm, we evaluated the statistical evaluation for 10 test samples, the severe biased and the moderate biased stream. Although the random bit stream has the biased characteristics. But the differential quantities are compensated using the randomized process by chaos function. Therefore in the randomness evaluation of hardware generator, the proposed randomized algorithm is always satisfied the randomness test condition.

This paper studies pulse-coupled network of digital spiking neurons and its basic dynamics. The neuron is constructed by coupling two shift registers and has a variety of spike-trains which correspond to digital codes through a inter-spike interval (ISI) modulation. The pulse-coupled network has master-slave configuration. All the spike-trains of neurons in the master side are multiplexed additionally and are transmitted to the slave side via single line. Neurons in the slave side are connected by dynamic winner-take-all function. As parameters are selected suitably, the slave can realize demultiplexing and master-slave synchronization is achieved. VHDL simulation is also discussed for FPGA implementation and this digital network is compared with an analog network.

Considering the first two generations of Artificial Neural Networks, Hopfield model is the only active system. Studying this type of network, a relation between this artificial neural network and the third generation, characterized by spiking neurons, was noticed. This paper presents the relationship between the Hopfield Neural Networks and the Pulsed Neural Networks. This relation is shown by the integration of the Hopfield neuron model, ending in an integrate-and-fire model, with the appropriate choice of the input kernels.

This paper addresses the problem of accelerating large artificial neural networks (ANN), whose topology and weights can evolve via the use of a genetic algorithm. The proposed digital hardware architecture is capable of processing any evolved network topology, whilst at the same time providing a good trade off between throughput, area and power consumption. The latter is vital for a longer battery life on mobile devices. The architecture uses multiple parallel arithmetic units in each processing element (PE). Memory partitioning and data caching are used to minimise the effects of PE pipeline stalling. A first order minimax polynomial approximation scheme, tuned via a genetic algorithm, is used for the activation function generator. Efficient arithmetic circuitry, which leverages modified Booth recoding, column compressors and carry save adders, is adopted throughout the design.

A novel CMOS four-quadrant analog-digital multiplier for implementing a programmable Cellular Neural Network (CNN) is presented. The circuit, which can be fabricated in a standard CMOS process, performs the four-quadrant weighting of interconnect signals. Using this multiplier a programmable CNN neuron can be implemented with little expense. Both simulation and test results are given for the circuit fabricated in a standard, mixed signal, 0.18m, CMOS process. According to this design, one input is analog voltage and the other input is digital signal. The linearity deviation is less than 1% in the dynamic range (1.0V,2.2V) centered on V=1.6V. The power supply voltage is 3.3V.