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Palabras clave – provistas por la editorial

triple modular redundancy; 65 nm CMOS technology; single event effects; radiation hardening by design; digital integrated circuits; fault injection; simulation; VHDL; open source tools; triple modular redundancy TMR; time redundancy (TR); TMR/Simplex; reliability improvement factor (RIF); half-duty limited DC-DC converter; total ionizing dose; system-level testing; point-of-load converter; radiation hardness assurance; system qualification; All-Digital; PLL; CDR; Single-Event Effects; radiation hardening; system-level tests; D Flip-Flop; heavy ion; radiation hardened; Single Event Upset; D-type flip-flop; single event transient; single event upset; quadrature; super-harmonic; LC-tank; Q-phase; VCO; QVCO; radiation; TID; SEE; X-ray; high energy physics; radiation hardened by design; 22-nm FD SOI; 28-nm FD SOI; Co-60; flip-flop (FF); radiation effects; ring oscillator (RO); static random-access memory (SRAM); total ionizing dose (TID); radiation effect; radiation test method; sensitive area; parasitic bipolar amplification; processor; laser test; generalized linear model; ensemble method; confidence interval; double-node upset (DNU); radiation-hardened latch; radiation hardening by design (RHBD); single event upset polarity; single-node upset (SNU); soft error; n/a