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Verification is a process, not a set of testbenches. Verification can be only accomplished through an independent path between a specification and an implementation. It is important to understand where that independence starts and to know what is being verified. Verification can be performed at various levels of the design hierarchy, with varying degrees of visibility within those hierarchies. I prefer a black-box approach because it yields portable testbenches. Augment with grey and white-box testbenches to meet your goals. Consider verification at the beginning of the design. If a function would be difficult to verify, modify the design to give the necessary observability and controllability over the function. Make your verification components reusable across different testbenches, across block and system-level testbenches and across different projects.

Despite reporting many false errors, linting and other static code checking technologies are still the most efficient mechanism for finding certain classes of problems. Simulators are only as good as the model they are simulating. Simulators offer many performance enhancing options and the possibility to co-simulate with other languages or simulators. Assertion-based verification is a powerful addition to any verification methodology. This approach allows the quick identification of problems, where and when they occur. Verification-specific SystemVerilog features offer an increase in productivity because of their specialization to the verification task and their support for coverage-driven random-based verification. Use code and functional coverage metrics to provide a quantitative assessment of your progress. Do not focus on reaching 100 percent at all cost. Do not consider the job done when you’ve reached your initial coverage goals. Use a source control system and an issue tracking system to manage your code and bug reports.

Model your clock signals in a module . Be careful about time resolution issues, delta cycle alignment and implicit synchronization of asynchronous signals. Encapsulate repetitive physical-level operations into bus-functional tasks. Collect all of the bus-functional tasks for a physical interface or protocol into a bus-functional model. Detect concurrent activation of bus-functional tasks within the same bus-functional model using a semaphore. Design an effective transaction-level interface with a suitable transaction completion and status notification mechanism. Provide callbacks in bus-functional models and response monitors to enable access to symbol-level protocol parameters and inject symbol-level errors.