Catálogo de publicaciones - libros

This chapter presents a complete outline for this Book. It explains the main goals pursued, the strategies chosen to achieve those goals, and a summary of the material to be covered throughout this Book.

In our Information Age, the need for protecting information is more pronounced than ever. Secure communication for the sensitive information is not only compelling for military or government institutions but also for the business sector and private individuals. The exchange of sensitive information over wired and/or wireless Internet, such as bank transactions, credit card numbers and telecommunication services are already common practices. As the world becomes more connected, the dependency on electronic services has become more pronounced. In order to protect valuable data in computer and communication systems from unauthorized disclosure and modification, reliable non-interceptable means for data storage and transmission must be adopted.

An FPGA is an integrated circuit that belongs to a family of programmable devices called Programmable Logic Devices (PLDs). An FPGA contains tenths of thousands of building blocks, known as (CLB) connected through programmable interconnections. Those CLBs can be reconfigured by the designers themselves resulting in a functionally new digital circuit, this way, virtually any kind of digital circuit can be implemented using FPGAs [11, 272, 304, 244].

The material presented in this Chapter, discusses several relevant mathematical concepts, fundamental for the understanding of elliptic curve public-key cryptosystems, the RSA algorithm, etc.. This material is also useful for a better understanding of the basic operations involved in the specifications of Rijndael algorithm (new Advanced Encryption Standard (AES)).

The modular exponentiation operation is a common operation for scrambling; it is used in several cryptosystems. For example, the Diffie-Hellman key exchange scheme requires modular exponentiation [64]. Furthermore, the ElGamal signature scheme [80] and the Digital Signature Standard (DSS) of the National Institute for Standards and Technology [90] also require the computation of modular exponentiation. However, we note that the exponentiation process in a cryptosystem based on the discrete logarithm problem is slightly different: The base (M) and the modulus (n) are known in advance. This allows some precomputation since powers of the base can be precomputed and saved [35]. In the exponentiation process for the RSA algorithm, we know the exponent (e) and the modulus (n) in advance but not the base (M); thus, such optimizations are not likely to be applicable.

In this Chapter we review some of the most relevant arithmetic algorithm on binary extension fields (). The arithmetic over () has many important applications in the domains of theory of code theory and in cryptography [221, 227, 380]. Finite field’s arithmetic operations include: addition, subtraction, multiplication, squaring, square root, multiplicative inverse, division and exponentiation.

This Chapter has two main purposes. The first purpose is to introduce readers to how hash functions work. The second purpose is to study key aspects of hardware implementations of hash functions. To achieve those goals, we selected MD5 as the most studied and widely used hash algorithm. A step-by-step description of MD5 has been provided which we hope will be useful for understanding the mathematical and logical operations involved in it. The study and analysis of MD5 will be utilized as a base for explaining the most recent SHA2 family of hash algorithms.

This chapter pretends to provide general guidelines for the efficient implementation of block ciphers in reconfigurable hardware platforms. The general structure and design principles for block ciphers are discussed. Basic primitives in block ciphers are identified and useful design techniques are studied and analyzed in order to obtain efficient implementations of them on reconfigurable devices. As a case of study, those techniques are applied to the Data Encryption Standard (DES), thus producing a compact DES core.

In this chapter we present some of the most common architectural alternatives to implement Advanced Encryption Standard (AES) in reconfigurable hardware. The first factor to be considered on implementing AES is the application. There are high speed applications like High Definition TV (HDTV) and video conferencing where high performance is required. The target throughput, expressed in gigabits per second (Gbps), must be specified, and to achieve such a high performance we can replicate several functional units to increase parallelism. That would however imply higher power and hardware area requirements.

In this chapter we discuss several algorithms and their corresponding hardware architecture for performing the scalar multiplication operation on elliptic curves defined over binary extension fields (). By applying parallel strategies at every stage of the design, we are able to obtain high speed implementations at the price of increasing the hardware resource requirements. Specifically, we study the following four different schemes for performing elliptic curve scalar multiplications,