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Título de Acceso Abierto
Desarrollo de encriptado AES en FPGA
Mónica Cristina Liberatori Oscar N. Bria Horacio A. Villagarcía Wanza
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Resumen/Descripción – provisto por el repositorio digital
The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. Synthesis results in the use of 460 logic cells and 4480 memory bits. The VHDL code was simulated using the test vectors provided in the AES submission package. The results are functionally correct. The architecture needs fewer logic cells than other ciphers and uses as few memory blocks as possible. The design goals were area and cost optimisation.Palabras clave – provistas por el repositorio digital
Ciencias Informáticas; Redes y Seguridad; Informática; Aplicación informática; Encriptación de datos
Disponibilidad
| Institución detectada | Año de publicación | Navegá | Descargá | Solicitá |
|---|---|---|---|---|
| No requiere | 2006 | SEDICI: Repositorio Institucional de la UNLP (SNRD) |
|
Información
Tipo de recurso:
tesis
Idiomas de la publicación
- español castellano
País de edición
Argentina
Fecha de publicación
2006-02
Información sobre licencias CC
