Catálogo de publicaciones - libros

A verifiably encrypted signature can convince the verifier that a given cipher-text is the encryption of a signature on a given message. It is often used as a building block to construct optimistic fair exchange. Recently, Gu gave an ID-based verifiably encrypted signature scheme and claimed that their scheme was secure in random oracle model. Unfortunately, in this works, we show that their scheme is insecure. And we can mount to universal forgery attack in their model. In other words, any one is able to forge a verifiably encrypted signature on arbitrary message . Subsequently, a novel verifiably encrypted signature scheme (VES) is proposed and the scheme is proven secure in random oracle model. Moreover, the size of verifiably encrypted signature in our scheme is shorter than that of Gu ’s signature.

An iterative modulo scheduling is very important for compilers targeting high performance multi-issue digital signal processors. This is because these processors are often severely limited by idle state functional units and thus the reduced idle units can have a positively significant impact on their performance. However, complex instructions, which are used in most recent DSPs such as , usually increase data dependence complexity, and such complex dependencies that exist in signal processing applications often restrict modulo scheduling freedom and therefore, become a limiting factor of the iterative modulo scheduler.

In this work, we propose a technique that efficiently reselects instructions of an application loop code considering dependence complexity, which directly resolve the dependence constraint. That is specifically featured for accelerating software pipelining performance by minimizing length of intrinsic cyclic dependencies. To take advantage of this feature, few existing compilers support a loop unrolling based dependence relaxing technique, but only use them for some limited cases. This is mainly because the loop unrolling typically occurs an overhead of huge code size increment, and the iterative modulo scheduling with relaxed dependence techniques for general cases is an NP-hard problem that necessitates complex assignments of registers and functional units. Our technique uses a heuristic to efficiently handle this problem in pre-stage of iterative modulo scheduling without loop unrolling.

A priority-driven scheduling algorithm is said to be if the start time (finish time) of jobs in the schedule where each job executes for its actual execution time is bounded by the start times (finish times) of jobs in the schedules where each job executes for its maximum/minimum execution time. In this paper, we study the predictability of a job-level dynamic priority algorithm, LLF (Least Laxity First), on multiprocessor real-time systems. We present a necessary and sufficient condition for a priority-driven algorithm to be start time (finish time) predictable. Then, in LLF scheduling, we show that both the start time and the finish time are predictable if the actual execution times cannot be known. However, solely the finish time is predictable if the actual execution times can be known.

Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low power-consumption, but also high computing performance. To enhance performance while hold energy constraints, some high-end embedded processors, therefore, adopt conventional features to exploit instruction-level parallelism and increase clock rates. The reorder buffer (ROB) and the register file are the two most critical components to implement these features. The cooperation of them, however, causes serious leakage power, especially for a large register file. In this paper, we propose a pure hardware approach to reduce the leakage power for the register file, such that more complex features (e.g., out-of-order execution, speculation execution, etc) can be applied to high-end embedded processors. In the proposed approach, we design a monitoring scheme in the pipeline datapath to identify the timing of powering up or powering down a register. Simulation results show that our approach saves at least 50% power consumption of the register file, with almost negligible performance lost.

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DDMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time stacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our call chain balancing (CCB) algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of run-time memory in the target code.

Currently the Java programming language is popularly used in Internet-based systems, mobile and ubiquitous devices because of its portability and programability. However, inherently its performance is sometimes very limited due to interpretation overhead of class files by Java Virtual Machines (JVMs). In this paper, as one of the solutions to resolve the performance limitation, we present code generation and optimization techniques for a Java-to-C translator. Our compiler framework translates Java bytecode into C codes with preserving Java’s programming semantics, such as inheritance, method overloading, virtual method invocation, garbage collection, and so on. Moreover, our compiler translates in Java into in C instead of and for better performance. Our runtime library fully supports Connected Limited Device Configuration (CLDC) 1.0 API’s.

With the increasing complexity of the real-time embedded software, the power consumption is becoming a real challenge in the system designs. In this paper, for modelling the component-based embedded software, the interface automata is extended by adding time intervals on the actions and assigning energy consumption rates on the states. The extensional formalism is called . Then the system designs are modelled by energy interface automaton networks which consist of a set of energy interface automata synchronized by shared actions. Based on analyzing the integer state space of the energy interface automaton networks and its compatible reachiability graph, we develop two algorithms for the problem of the minimal energy consumption calculation and the maximal energy consumption verification respectively.

Programmable vertex processing unit increases the programmability and enables customizations of transformation and lighting in the graphics pipeline. Furthermore, it offers various effects such as procedural vertex animation and deformation, which were impossible to handle in fixed vertex processing. Since it is hard to find a programmable graphics hardware for the embedded systems such as mobile phones, we’ve designed and implemented a programmable vertex processing unit based on the OpenGL ES 2.0 specification. In this paper, we explain the architecture, instruction format, implementation and test results of our vertex processing unit.

This paper presents the design of a high performance energy-aware whole-system emulator – SkyEye. Several optimization and novel energy estimation methods used in SkyEye are proposed. By using novel searching strategy for Translated Block (TB), SkyEye save the time to find proper translated block. SkyEye uses Basic Equal Length Unit (B-ELU) method, and dynamic binary translation to reduce the simulation and energy evaluation time. The performance model of B-ELU is built to get the best length of translated block. In addition, the simulator automatically detects the voltage/frequency variation, and adjusts the energy estimation model accordingly. Using these methods, SkyEye which simulates ARM CPU based hardware system achieves marvelous performance and energy-aware statistic capability in experiments.

Runtime data alignment has been paid attention recently since it can allocate data segment to processors dynamically according to applications’ requirement. One of the key optimizations of this problem is to schedule simultaneous communications to avoid contention and to minimize the overall communication costs. The NP-completeness of the problem has instigated researchers to propose different heuristic algorithms. In this paper, we present an algorithm independent technique for optimizing scheduling stability of different scheduling heuristics. The proposed technique introduces a new scheduling policy, Local Message Reduction (LMR), to obtain better communication schedule adaptive to different environments. o evaluate the performance of the proposed technique, we have implemented LMR along with two existing algorithms, the two-phase degree reduction and the list scheduling algorithms. The experimental results show that the proposed technique is effective in terms of scheduling stability, communication efficiency and easy to implement.