Catálogo de publicaciones - libros

This paper discusses efficiency measures for the evaluation of high performance multimedia systems on a chip , considering a throughput rate , chip size , power dissipation , and a flexibility criterion . Based on the analysis of recently published multimedia chips, the paper shows equivalences between the ratio of over , a weighted sum on , , , and a fuzzy multicriteria analysis on , , . The paper indicates the fuzzy multicriteria analysis as generalization of the other efficiency measures, which can be easily applied to multiple cost and performance criteria. Because of the application of fuzzy set theory, the multicriteria approach supports quantitative criteria with a physical background as well as qualitative criteria by linguistic variables.

This paper presented a latency and power model to determine the bus configuration of a target SoC system at its early design stage. The latency model analyzed the latencies of an on-chip bus and provided throughput reflecting the bus configuration. The power model provided power estimation based on the pre-determined bus architecture. This paper showed new parameters to devise the proposed models such as bus usage, active bridge ratio, etc. Moreover, we evaluated the throughput of the bus and compared this with the required throughput of the target SoC, including a number of real IPs. This target SoC was configured based on the estimation results obtained from the proposed bus model. This estimation were compared with the simulation results of target SoC design for verifying the accuracy of the proposed model. The evaluation showed that the accuracies of the proposed model for the latency and the power model were over 85% and 92%, respectively. This result set the standard for an efficient bus structure for a SoC design.

In this paper we present a general framework for the support of flexible models representation and execution in the context of SoC design space exploration. Coming as a C++ library, it allows the user to gather models from its own and existing models into larger and more complete models. Compared to existing modeling systems we introduce the notion of that allows the user to turn any parameter appearing in a model into the output : it increases the model flexibility and enables its reuse in very different problems. Aside from providing specification and execution support, the framework also permits dynamic model sensitivity analysis and efficient parameter sensitivity analysis for closed-formed models. Through this paper we explain our original 3-level hierarchical representation of model and explain meanwhile how it offers flexibility and model robustness using a XML schema grammar.

The Sesame modeling and simulation framework aims at early and thus efficient system-level design space exploration of embedded multimedia system architectures. So far, Sesame only supported performance evaluation when mapping a single application onto a (multi-processor) architecture at the time. But since modern multimedia embedded systems are increasingly multi-tasking, we need to address the modeling of effects of executing multiple applications concurrently in our system-level performance models. To this end, this paper conceptually describes two multi-application workload modeling techniques for the Sesame framework. One technique is based on the use of synthetic application workloads while the second technique deploys only real application workloads to model concurrent execution of applications. For illustrative purposes, we also present a preliminary case study in which a Motion-JPEG encoder application is executed concurrently with a small synthetic producer-consumer application.

Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed.

This paper evaluates commonly used models for function unit pipeline resource conflict detection in processor simulation: a resource vector based-model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides equal simulation speed when compared to the actively initialized FSA. Our benchmarks show at best 23 percent improvement to the initialization time.

This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.

In this paper we describe an efficient data fetch circuitry for retrieving several operands from a n-bank interleaved memory system in a single machine cycle. The proposed address generation (AGEN) unit operates with a modified version of the low-order-interleaved memory access approach. Our design supports data structures with arbitrary lengths and different (odd) strides. A detailed discussion of the 32-bit AGEN design aimed at multiple-operand functional units is presented. The experimental results indicate that our AGEN is capable of producing 8 x 32-bit addresses every 6 ns for different stride cases when implemented on VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using trivial hardware resources.

This paper proposes a multithreaded Java processor as an IP core for Altera’s System-on-Programmable-Chip environment. The processor core is an enhancement of the earlier developed multithreaded Java processor named Komodo. It features a real-time capable garbage collection and integrated real-time scheduling schemes. Hence, it is suitable for embedded hard, soft, and non real-time systems. The facts that the processor is designed as an IP core and that it is a special Java processor makes both easier: hardware design and software development.

A conflict resolving parallel data memory system for Transport Triggered Architecture (TTA) is described. The architecture is generic and reusable to support various application specific designs. With parallel memory, more area and power consuming multi-port memory can be replaced with single-port memory modules. Number of ports can be increased over what is available on a design library for multi-port memories. In an FFT TTA example, dual-port data memory was replaced by the proposed architecture. To avoid memory conflicts, the original code was rescheduled and the TTA core was regenerated for the new schedule. The original memory required an area higher by a factor of 3.38 and energy higher by a factor of 1.70. In this case, the energy consumption of the processor core increased so that system energy consumption remained about the same. However, the original system required an area higher by a factor of 1.89.

The Instruction-Set extension problem has been one of the major topics in the last years and it is the addition of a set of new complex instructions to a given Instruction-Set. This problem in its general formulation requires an exhaustive search of the design space to identify the candidate instructions. This search turns into an exponential complexity of the solution. In this paper we propose an algorithm for the generation of Multiple Input Single Output instructions of variable size which can be directly selected or combined for Instruction-Set extension. Additionally, the algorithm is suitable for inclusion in a design flow for automatic generation of MIMO instructions. The proposed algorithm is not restricted to basic-block level and has linear complexity with the number of processed elements.