Catálogo de publicaciones - libros

This paper presents two additional strategies to reduce simulation time for Bayesian based stopping rules in VHDL model verification. The first is that a semi-random variable is defined and the data staying in the semi-random variable range are skipped when stopping rule is running, and a turning point that can partition a random variable into a semi-random and a genuine random variable is chosen. The second is that the old values of parameters are kept when phases of stopping rule change. 12 VHDL models are examined, and the simulation results demonstrate that more than approximately 25% of clock cycles are reduced when using the two proposed strategies with 0.6% branch coverage rate loss.

Hardware-software partitioning is one of the most crucial steps in the design of embedded systems, which is the process of partitioning an embedded system specification into hardware and software modules to meet performance and cost goals. A majority of former work focuses on the problem of meeting timing constraints under minimizing the amount of hardware or minimizing time under hardware area constraints. The trends towards energy-efficient design of distributed embedded systems indicate the need for low power hardware-software partitioning algorithms, which are not enough emphasized so far. In this paper, we design tabu search on a chaotic neural network to solve the low power hardware-software partitioning problem. By introducing chaotic dynamics and utilizing the refractory effects of neurons as the tabu effects, the realized tabu search gets partitioning result with lower energy consumption, when compared with genetic algorithm.

Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses the generation of mappable CIs on an RFU. In this paper, our proposed RFU architecture for an adaptive dynamic extensible processor is described. Then, an integrated framework for temporal partitioning and mapping is presented to partition and map the CIs on RFU. In this framework, two mapping aware temporal partitioning algorithms are used to generate CIs. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. Using this framework brings about more speedup for the extensible processor.

The effective scheduling of transactions has a great potential for SoC functional verification. Petri nets have proven to be a promising technique for solving scheduling problem. This paper aims at presenting a Petri-net based approach to the scheduling of transactions generated by a test-case generator. Firstly, an extended scheduling timed Petri nets (ESTPN) model is given to support transaction scheduling. Secondly, the short term of ‘scheduling of transactions problem’ is formulated by means of an ESTPN which can accommodate various scheduling policies. Finally, transactions scheduling schemes and scheduling algorithm based on ESTPN are given and cases are studied.

Software programmers want to manage pure software, not hardware-software entanglements. Unfortunately, traditional development methodologies cannot clearly separate hardware and software in embedded system development process. We propose a ; we call it HINGE. After receiving device specifications including device usage rules for each device, HINGE automatically generates device API, device driver, and device controller for each device. In addition, HINGE equips device APIs to check the device usage rules at run-time. Consequently, HINGE gives support to not only fast prototyping but also device usage rule-debugging in embedded software.

In this paper, a general fault-tolerant framework adopting a more rigid fault model for VLIW data paths is proposed. The basic idea used to protect the data paths is that the execution result of each instruction is checked immediately and if errors are discovered, the instruction retry is performed at once to overcome the faults. An experimental architecture is developed and implemented in VHDL to analyze the impacts of our technique on hardware overhead and performance degradation. We also develop a comprehensive fault tolerance verification platform to facilitate the assessment of error coverage for the proposed mechanism. A paramount finding observed from the experiments is that our system is still extremely robust even in a very serious fault scenario. As a result, the proposed fault-tolerant VLIW core is quite suitable for the highly dependable real-time embedded applications.

The paper presents a new stochastic model for mesh-based reconfigurable computing. Under the conditions of several statistical assumptions, closed formulae of probability and mathematical expectation are derived for each type of connections. Both the theoretical deduction and simulation results are given to verify our approach. The elementary research can be applied to implement and optimize the interconnect resource of mesh-based reconfigurable computing.

A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.

In RFID (Radio Frequency IDentification) systems, a tag reader communicates with tags, reads their identification codes, and accesses their related database through network infrastructure. There are many research activities in RFID systems for industrial applications such as delivery, manufacturing, and so on, but there is few on mobile devices such as cellular phones and PDAs. This paper presents architecutre of a multi-protocol RFID reader on mobile devices. We have considered several design parameters, such as low power consumption, cost effectiveness and flexibility. We prototyped our system on the ARM-based Excalibur FPGA with iPAQ PDA, and also a chip with 0.18um technology for verification of our architecture.

When flash memory is used as a storage in embedded systems, block level translation layer is required between conventional filesystem and flash memory chips due to its physical characteristics. A far more efficient use of it is the design of a filesystem itself without no extra layer of translation. However, since flash filesystem does not use block device layer, it cannot utilize deferred I/O although deferred I/O enhances write latency by delaying the flushing jobs. Linux operating system generally uses the write back routine for deferred I/O using kernel thread, which writes back dirty pages and buffers through the block device layer. In this paper, we design and implement efficient I/O for JFFS2 flash filesystem based on flash memory. For this, we first analyze the write procedure of JFFS2 filesystem in detail, and derive the drawback and overhead. Then, we design the flash write back routine for deferred I/O. We apply it to the Linux JFFS2 by implementing and _ kernel thread. The designed flash write back routine can reduce average write latency when the kernel buffers are enough to get the users data.