Catálogo de publicaciones - libros

In this paper, we propose the markup language framework and its associated HTTP protocol extension to support data integrity for active web intermediaries. There are three aspects that our language framework would like to focus on. Firstly, the content server can specify its intended authorization and task to multiple web intermediary proxies in its content objects easily. Secondly, a web intermediary performing value-added services through content adaptation needs to leave its modification footprints for possible verification by client. Thirdly, a client is facilitated to verify the received message with the server’s authorizations and intermediaries’ footprints without affecting his perceived web latency. We demonstrate the feasibility and practicability of this language framework through its actual implementation.

The paper addresses batch verification to reduce large computational cost when many digital signatures are verified together, and then presents bad signature identification in the batch verification of signatures too when there is one bad signature in the batch. Our method, (Exponent Based Verifier), can verify a batch of signatures and identify a bad signature using one modular exponentiation and modular multiplications where is the number of signatures in the batch instances. Simulation results also show the proposed method reduces considerably the number of modular multiplications compared with the existing methods.

In this paper, we propose a resource management system in Grid computing in order to specify system Quality of Service (QoS) requirements for dynamic and complex emerging applications. Our approach is based on the among application components to specify the probability of system QoS requirements for the emerging application. Experimental results show that our application scheduling based on can achieve scheduling and managing emerging applications to satisfy a client’s quality of service in Grid computing. The results also show significant improvement of performance comparing to cluster distribution and random distribution scheduling approaches.

In this paper, we propose a hierarchical architecture for grouping peers into clusters in a large-scale BitTorrent-like underlying overlay network in such a way that clusters are evenly distributed and that the peers within are relatively close together. We achieve this by constructing the CBT (Clustered BitTorrent) system with two novel algorithms: a peer joining algorithm and a super-peer selection algorithm. Proximity and distribution are determined by the measurement of distances among peers. Performance evaluations demonstrate that the new architecture achieves better results than a randomly organized BitTorrent network, improving the system scalability and efficiency while retaining the robustness and incentives of original BitTorrent paradigm.

Web services provide a useful means to integrate heterogeneous applications distributed over the Internet based on XML and Web technologies. This paper presents an approach to execute hierarchically interacting web services efficiently. We provide a system architecture which can distribute invocations of web services over service providers by exploiting intensional XML messages embedding external web service calls. We also propose a greedy heuristic algorithm to generate an efficient strategy of executing web service calls, which can improve overall performance of distributed web service systems on the Internet.

Recently, flash memory is widely adopted in embedded applications since it has several strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristic, namely “erase before write”, it requires a software layer called FTL (Flash Translation Layer). This paper surveys the state-of-the-art FTL software for flash memory. This paper also describes problem definitions, several algorithms proposed to solve them, and related research issues. In addition, this paper provides performance results based on our implementation of each of FTL algorithms.

The majority of scientific and Digital Signal Processing (DSP) applications are recursive or iterative. Transformation techniques are generally applied to increase parallelism for these nested loops. Most of the existing loop transformation techniques either can not achieve maximum parallelism, or can achieve maximum parallelism but with complicated loop bounds and loop indexes calculations. This paper proposes a new technique, , that can maximize parallelism while maintaining the original row-wise execution sequence with minimum overhead. Loop striping groups iterations into stripes, where a stripe is a group of iterations in which all iterations are independent and can be executed in parallel. Theorems and efficient algorithms are proposed for loop striping transformations. The experimental results show that loop striping always achieves better iteration period than software pipelining and loop unfolding, improving average iteration period by 50% and 54% respectively.

Broadcast and mobile phone technologies have now combined to provide wireless multimedia services. 3GPP2 has introduced the Broadcast and Multicast Services (BCMCS) architecture in a 3G wireless network. BCMCS are capable of supplying multimedia content, which requires successive frames to arrive within a specific time interval. We analyze the execution time of Reed-Solomon decoding, which is the MAC-layer forward error correction scheme used in cdma2000 1xEV-DO BCMCS, under different air channel conditions. The results show that the time constraints of MPEG-4 cannot be guaranteed by Reed-Solomon decoding when the packet loss rate (PLR) is high, due to its long computation time on current hardware. To alleviate this problem, we propose three error control schemes. Our static scheme bypasses Reed-Solomon decoding at the mobile node to satisfy the MPEG-4 time constraint when the PLR exceeds a given boundary. Our second, dynamic scheme corrects errors in a best-effort manner within the time constraint, instead of giving up altogether when the PLR is high. The third, video-aware dynamic scheme fixes errors in a similar way to the dynamic scheme, but in a priority-driven manner which improves the quality of the final video. Extensive simulation results show the effectiveness of our schemes compared to the original FEC scheme.

Behavior, situations and environmental changes in embedded software, such as robot software, are hard to expect at software design time. To deal with dynamic behavior, situations and environmental changes at runtime, current software engineering practices are not adequate due to the hardness of software modification. An approach to resolve this problem could be making software really “” that enables runtime software modification. We developed a practical framework called SHAGE(Self-Healing, Adaptive, and Growing SoftwarE) to implement reconfigurable software in home service robots. SHAGE enables runtime reconfiguration of software architecture when a service robot encounters unexpected situations or new user requirements. This paper focuses on designing reconfigurable software architecture, so called, dynamic software architecture. We also conducted a case study on a home service robot to show applicability of the framework. The results of the study shows practicality and usefulness.

Certain hard real-time tasks demand precise timing of events, but the usual software solution of periodic interrupts driving a scheduler only provides precision in the millisecond range. NOP-insertion can provide higher precision, but is tedious to do manually, requires predictable instruction timing, and works best with simple algorithms.

To achieve high-precision timing in software, we propose instruction-level access to cycle-accurate timers. We add an instruction that waits for a timer to expire then reloads it synchronously. Among other things, this provides a way to exactly specify the period of a loop.

To validate our approach, we implemented a simple RISC processor with our extension on an FPGA and programmed it to behave like a video controller and an asynchronous serial receiver. Both applications were much easier to write and debug than their hardware counterparts, which took roughly four times as many lines in VHDL. Simple processors with our extension brings software-style development to a class of applications that were once only possible with hardware.