Catálogo de publicaciones - libros

Flash memory’s adoption in the mobile devices is increasing for various multimedia services such as audios, videos, and games. The traditional research issues such as out-place update, garbage collection, and wear-leveling are important, the fast initialization and response time issues of flash memory file system are becoming much more important than ever because flash memory capacity is rapidly increasing. In this paper, we propose a fast initialization technique and an efficient memory management technique for fast response time in log-based flash memory file systems. Our prototype is implemented based on a well-known log-based flash memory file system YAFFS2 and the performance tests were conducted by comparing our prototype with YAFFS2. The experimental results show that the proposed initialization technique reduced the initialization time of the log-based flash memory file system regardless of unmounting the file system properly. Moreover our prototype outperforms YAFFS2 in the read I/O operations and the forward/backward seek I/O operations by way of our proposed memory management technique. This technique is also able to be used to control the memory size required for address mapping in flash memory file systems.

The multi-layer AHB busmatrix (ML-AHB busmatrix) proposed by ARM is a highly efficient on chip bus that allows parallel access paths between multiple masters and slaves in a system. In this paper, we present one way to improve the arbiter implementation of the ML-AHB busmatrix. We employ the masking mechanism which does not impose any restrictions on arbitration scheme. Therefore, the proposed scheme is applied to the implementation of busmatrixes to support the transaction based arbitrations as well as the transfer based arbitrations. In addition, we could not only enhance the throughput of bus system but also reduce the total area, clock period and power consumption. Experimental results show that the throughput of our busmatrix based on the transfer based fixed priority (round robin) arbitration scheme is increased by 41% (18%) compared with that of the equivalent busmatrix of ARM. Moreover, we could reduce the total area, clock period and power consumption by 22%, 28% and 19% (12%, 15% and 13%) respectively, compared with the busmatrix employing the transfer based fixed priority (round robin) arbitration scheme of ARM.

Routers are pivotal modules in any networks-on-chip (NoC)-based design. In order to achieve an efficient router design, the size of the queue must be optimally chosen. The choice of queue size affects packet loss probability and impacts the silicon area of the overall NoC-based design. For these reasons, a modeling process is needed to obtain an early estimation of the optimum queue size that matches packet arrival rate, number of traffic sources, and the permissable loss probability. In this paper, we use Markov chain analysis to model an M/D/1/B queue for an NoC output-queuing router. We explain how to optimally chose the queue size using pre-defined design parameters that match different target applications. Our model is validated with a prototype router implementation on FPGA.

In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing their corresponding data flow graph (DFG) on the accelerator brings about more speedup. In this paper, we intend to present our motivations for handling control instructions in DFGs and extending them to Control DFGs (CDFGs). In addition, basic requirements for an accelerator with conditional execution support are proposed. Moreover, some algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural specifications. To show the effectiveness of the proposed ideas, we applied them to the accelerator of an extensible processor called AMBER. Experimental results represent the effectiveness of covering control instructions and using CDFGs versus DFGs.

Recently, the continuously growing capacity of FPGAs has enabled us to place floating-point arithmetic IPs on FPGAs. The required area for floating-point computations, however, is still high. This paper presents a case study on behavioral synthesis of double-precision floating-point adders and adder/subtracters for FPGAs. With function-level transformations, we design totally 15 adders and 21 adder/subtracters from addition and subtraction functions written in C. Our experimental results show that the circuit area is reduced by 58%, the execution time is shortened by 47% and the area-delay product is improved by 69%. Through the case study, we show the effectiveness of behavioral synthesis with function-level transformations for designing complex arithmetic circuits.

Code size is becoming an important design factor in the embedded domain. To deal with this problem, many embedded RISC processors support a dual-width instruction set. Mixed code generation is also introduced in expectation of achieving both higher code density from the narrow instruction set (usually 16 bits) and good performance from the normal one (usually 32 bits), with little extra cost. To a certain application domain, processors can combine an efficient general purpose instruction set and a narrow instruction set tailored to the particular applications. Since the design of instruction set is highly related to the compiler and the application programs, a feedback driven technique will be a good choice. In this paper, we introduce a framework of automatic narrow instruction set design. The instructions are described in our Instruction Set Description Template (ISDT). Given a set of application programs, the design tool will iteratively use the suggested narrow instruction set represented in ISDT to do mixed-code generation and to update the narrow instruction set according to the evaluation feedback, thus to get an ultimate fine narrow instruction set without human designer’s involvement. We describe our method in detail by example of designing narrow instruction set for UniCore with the mediabench as the application set, and show its usefulness through the experiments.

This paper presents a hardware/software cosimulator for multiprocessor embedded systems. Our cosimulator consists of multiple software simulators each of which simulates a set of application tasks together with an RTOS running on a processor, multiple hardware simulators and a cosimulation backplane. All of the simulators are executed concurrently with communication. Our cosimulator supports two types of communication; one is based on Remote Procedure Call (RPC), and the other is based on a shared memory on a host computer. Using the cosimulator, we successfully performed cosimulation of an MPEG encoder/decoder system with two processors and some peripheral circuits.

Over recent years automated face detection and recognition (FDR) have gained significant attention from the commercial and research sectors. This paper presents an embedded face detection solution aimed at addressing the real-time image processing requirements within a wide range of applications. As face detection is a computationally intensive task, an embedded solution would give rise to opportunities for discrete economical devices that could be applied and integrated into a vast majority of applications. This work focuses on the use of FPGAs as the embedded prototyping technology where the thread of execution is carried out on an embedded soft-core processor. Custom instructions have been utilized as a means of applying software/hardware partitioning through which the computational bottlenecks are moved to hardware. A speedup by a factor of 110 was achieved from employing custom instructions and software optimizations.

This paper introduces improved fission rule depending on SNNR (Signal Plus Noise to Noise Ratio) and fuzzy value for simultaneous multi-modality, and suggests the Fusion User Interface (hereinafter, FUI) including a synchronization between audio-gesture modalities, based on the embedded KSSL (Korean Standard Sign Language) recognizer using the WPS (Wearable Personal Station for the next generation PC) and Voice-XML. Our approach fuses and recognizes 62 sentential and 152 word language models that are represented by speech and KSSL, then translates recognition results that is fissioned according to a weight decision rule into synthetic speech and visual illustration (graphical display by HMD-Head Mounted Display) in real-time. The experimental results, average recognition rates of the FUI for 62 sentential and 152 word language models were 94.33% and 96.85% in clean environments (e.g. office space), and 92.29% and 92.91% were shown in noisy environments.

In this paper, we discuss the user-customized interaction for intelligent home environments. The interactive system is based upon the integrated techniques using both speech and face recognition. For essential modules, the speech recognition and synthesis were basically used for a virtual interaction between user and the proposed system. In experiments, particularly, the real-time speech recognizer based on the HM-Net(Hidden Markov Network) was incorporated into the proposed system. Besides, the face identification was adopted to customize home environments for a specific user. In evaluation, the results showed that the proposed system was useful and easy to use for intelligent home environments, even though the performance of the speech recognizer was not better than the simulation results owing to the ambient noisy environments.