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Recent embedded systems are composed of many components, and each component is an open system, and it has both real-time properties and uncertainties. We specify each component using timing constraints and probabilities, and compose systems from all the components. In order to treat them, we develop the followings: First we develop probabilistic timed game automata based on a probabilistic timed game as a computational model. Next we develop probabilistic timed game verification.

The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference is. To expand the design space and manage delay/area tradeoffs, we propose new adder architecture and a design methodology. The proposed adder architecture, named heterogeneous adder , decomposes an adder into blocks (sub-adders) consisting of carry-propagate adders of different types and precision. The flexibility in selecting the characteristics of sub-adders is the basis in achieving adder designs with desirable characteristics. We consider the area optimization under delay constraints and the delay optimization under area constraints by determining the bit-width of sub-adders using Integer Linear Programming. We demonstrate the effectiveness of the proposed architecture and the design method on 128-bit operands.

In this paper, we propose a real-time video watermarking chip and system which is hardware based watermark embedding system of SD/HD (standard definition/high definition) video with STRATIX2 FPGA device from ALTERA. There was little visual artifact due to watermarking in subjective quality evaluation between the original video and the watermarked one. Embedded watermark was all extracted after a robustness test called natural video attacks such as A/D (analog/digital) conversion and MPEG compression. Our implemented watermarking hardware system can be useful in movie production and broadcasting companies that requires real-time based copyright protection system.

In this paper, we propose a novel compressed cache hierarchy that uses a unified compression algorithm in both L1 data cache and L2 cache, called Simple Frequent Pattern Compression(S-FPC). This scheme can increase the cache capacity of L1 data cache and L2 cache without any sacrifice of the L1 cache access latency. The layout of compressed data in L1 data cache enables partial cache line prefetching and does not introduce prefetch buffers or increase cache pollution and memory traffic. Compared to a baseline cache hierarchy not supporting data compression in cache, on average, our cache hierarchy design increases the average L1 cache capacity(in terms of the average number of valid words in cache per cycle) by about 33%, reduces the data cache miss rate by 21%, and speeds up program execution by 13%.

Function inlining is a widely known technique that has been adopted in compiler optimization research domain. Inlining functions can eliminate the overhead resulted from function calls, but with inlining, the code size also grows unpredictably; this is not suitable for embedded processors whose memory size is relatively small. In this paper, we introduce a novel function inlining approach using the heuristic rebate_ratio, functions to be inlined are selected according to their rebate_ratios in a descending way. This kind of code optimization operation works at the source code level. Comparing with other algorithms, it is easier to implement. Our target is to get an optimal result of function inlining which can achieve the maximum performance improvement while keeping the code size within a defined limit.

In this paper, we propose a model to identify the cost of block cleaning of Flash memory. The model defines three performance parameters, namely, utilization, invalidity, and uniformity and presents a formula for estimating the block cleaning cost based on these parameters. Then, we design a new modification-aware (MODA) page allocation scheme which can improve the block cleaning cost by enhancing uniformity of Flash memory. Real implementation experiments conducted on an embedded system show that the MODA scheme can reduce block cleaning time by up to 43 seconds (with an average of 10.2 seconds) compared to the traditional sequential allocation scheme that is used in YAFFS.

Commonly, embedded file systems reside in main memory to manage the external memory such as flash memory in embedded systems. With the progress of hardware of embedded systems, the gap of speed between main memory and CPU is becoming larger and larger. The traditional embedded file systems can not be able to support real-time response enough for their main memory management policy. A new type of embedded file system is presented to provide more real-time performance. This new embedded file system, SPM file system, is based on the internal SRAM on chip and is able to reduce response time.

Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, low-power consumption, and none-volatile properties, However, due to the very distinct characteristics of flash memory, disk based systems and applications may result in severe performance degradation when directly adopting them on flash memory storage systems. Especially, when a B-tree is constructed, intensive overwrite operations may be caused by record inserting, deleting, and its reorganizing, This could result in severe performance degradation on NAND flash memory because of its distinct characteristics. In this paper, we propose an efficient buffer management scheme, called IBSF, which eliminates redundant index units in the index buffer and then delays the time that the index buffer is filled up. Consequently, IBSF significantly reduces the number of write operations to a flash memory when constructing a B-tree. We also show that IBSF yields a better performance on a flash memory by comparing it to the related technique called BFTL through various experiments.

Embedded software requires concurrency formalisms other than threads and mutexes used in traditional programming languages like C. Actor-oriented design presents a high level abstraction for composing concurrent components. However, high level abstraction often introduces overhead and results in slower system. We address the problem of generating efficient implementation for the systems with such a high level description. We use partial evaluation as an optimized compilation technique for actor-oriented models. We use a helper-based mechanism, which results in flexible and extensible code generation framework. The end result is that the benefit offered by high level abstraction comes with (almost) no performance penalty. The code generation framework has been released in open source form as part of Ptolemy II 6.0.1.

Some traditional optimizations improve the performance of pro-cessors, but consume the higher power dissipation. We study this trade-off using software prefetching as performance-oriented optimization technique. We first demonstrate that software prefetching provides a significant performance boost with the higher power on several memory-intensive benchmarks. However, when we combine software prefetching with dynamic voltage/frequency scaling (DVFS), the performance gain can be achieved without power increase, which is called a power-aware approach. Besides reducing power dissipation through DVFS, we also improve the performance through adjusting the prefetch distance. A modified SimpleScalar/Wattch is used to evaluate our power-aware software prefetching. Experimental results show this optimization approach is effective to guarantee no power increase due to prefetching and improve the performance of software prefetching.