Catálogo de publicaciones - libros

Web forums and online communities are becoming increasingly important information sources. While there are significant research works on classification of Web pages, relatively less is known on classification of online discussions. By observing the special nature of user participation in web communities, we propose classification methods based on user participation and text content of online discussions. Support vector machines have been employed in this study to classify and analyze discussions based on content and participation. It is found that the accuracy of using participation as classification features can be very high in certain communities. The use of high-dimensional classifier can be effective in enhancing retrieval and classification of online discussion topics.

This paper suggests a brokering process in which individual truckers participate in the process of matching trucks with freight. To maximize the total profit of trucks, a mathematical model is formulated for matching trucks with freight. It is shown that, by Lagrangean relaxation, the matching problem can be decomposed into a master problem and multiple sub-problems. This paper proposes a brokering process, based on the subgradient optimization technique, in which an optimality of individual truckers as well as the system optimality of truckers is satisfied. The effects of various practical considerations on the performance of the suggested brokering process are tested numerically and by using a simulation study.

This paper proposed a novel method of applying support vector machine for multi-class problem based on fuzzy integral. Firstly, the fuzzy measure of each binary classifier is constructed based on its classification accuracy during training and its agreement degrees to other support vector machines. Then the testing instances are classified by calculating the fuzzy integral between the fuzzy measures and the outputs of the binary support vector machines. The experiment results on iris and glass datasets from UCI machine learning repository and real plane dataset show that the new method is effective. And the experiment results ulteriorly indicate that the method with Choquet fuzzy integral has better performance than that with Sugeno integral.

This paper proposes a low-power high-speed CMOS analog two- input/one-output neuro-fuzzy chip, the basic blocks of which are Gaussian membership function circuit, minimization circuit, and a centroid algorithm defuzzification circuit. This chip has been fabricated in 0.6- μ m mixed-signal CMOS technology. Experiment and HSPICE simulation results show that because the compact structures and high-precision of the blocks the system not only consumes little power but also can be directly tuned by the weights calculated through the software such as Matlab.

This paper presents a new technique for solving the unsupervised clustering problem using a pulse based RBF neural network that is optimized by a genetic algorithm. In this new approach, the neuron encodes the information using the firing times of pulses that are generated by the neurons. Due to hardware’s speed advantage and its ability to parallelize along with reprogramability and reconfigurability, the field programmable gate array (FPGA) is used for implementing the proposed approach on-chip. The developed on-chip system is capable of solving various problems requiring large data set in real time. Experimental verification using a sample data set and Fisher’s Iris data set has shown the feasibility of the developed system.

Semiconductor Technology and multimedia communication has been developed to interest in high quality video and multi channels audio. Especially, it is trend to important technology so that DVD market grows rapidly. Mpeg audio standard is available support for any bit rate. In this paper, the design of Field Programmable Gate Array(FPGA) is presented mpeg audio synthesis filter by Distributed Arithmetic Look Up Table(DALUT) method. In order to design for high speed filter that operated from 10MHz to 30MHz and DALUT is used instead of multiplier. In this paper, the output is designed by VHDL and is verification using C language. VHDL simulation used Model-sim SE 5.7f and synthesis is used Synplify Pro 7.2Ver. Target library is used XC4010E, XC4020EX, XC4052XL and P&R tool used XACT M1.4.

To satisfy the requirement of embedded video encoder in various scenarios, an embedded universal video coding system based on embedded processors is proposed in this paper, which combines the advantages of multi processors in single architecture. According to different channels, two feasible solutions are given to avoid the overflow and underflow of buffer while transmitting the compressed data. Due to limited computational resources and real-time application requirement, each module of the MPEG-4 codec is reviewed and efficiently implemented based on the embedded hardware platform. Experimental results show that the embedded system can successfully be used for real-time application.

In this paper the effect of steady and relaxation oscillation in optical fiber based on neural networks and hardware implementation is described. The inherent optical feedback by the backscattered Stokes wave in optical fiber leads to instabilities in the form of optical chaos. The controlling of chaos induced transient instability in Brillouin-active fiber based smart structures leads to neural networks with steady and relaxation oscillations. Controlled chaotic instabilities can be used for optical logic and computations and optical sensing. It is theoretically possible to apply the multi-stability regimes as an optical memory device for encoding and decoding and complex data transmission in optical systems. These memories can be estimated as an optical logic function used for all-optic in-line switching, channel selection, oscillation, optical logic elements in optical computation with neural network application.

This paper presents a miniature device, which is used for stimulating to and recording from the brain of an animal, based on system on chip (nRF24E1). Its performance is validated by in vivo experiments, in which rats are trained to run down a maze to respond to auditory instruction cues by turning right or left in order to get an electrical stimulation ‘virtual reward’, and by comparing spikes recorded from the brain of rats between our device and a commercially available device (Spike2, Cambridge Electronic Design Ltd.). Results show that our device can work reliably and stably, and with notable characteristics of light weight (9g, without battery), simplicity and practicality.

This paper reports the implementation of an SoC (System on a Chip) IP(Intellectual Property) design for an Image Grabber that is capable of 2D scanning. The vast improvements in integrated circuit technology and semiconductor industry have allowed complicated hardware systems to be implemented into a single Chip. Previously, hardware designed by external buses was slow. However, the speed of the system has been improved by peripheral logics that are designed on a single chip. In addition, both hardware and software can be constructed together resulting in a significant decrease in research and development time. Four IPs were created in this study. I2C IP was developed for the Image Decoder. The NTSC analog signal from a CCD camera was converted to YUV422 using an image decoder and stored in a frame buffer by IMAGE IP. TFT-LCD IP was developed to display the data on an LCD. A robot IP was developed to control a perpendicular coordinate robot. Finally, system level software and PC software was developed to examine the SoC system.