Catálogo de publicaciones - revistas

<jats:p>This article gives an overview of a diverse selection of currently used second-generation image coding techniques. These techniques have been grouped into similar categories in order to allow a direct comparison among the varying methods. An attempt has been made, where possible, to expand upon and clarify the details given by the original authors. The relative merits ans shortcomings of each of the techniques are compared and contrasted.</jats:p>

<jats:p> In this article we present a comprehensive survey of various approaches for the verification of cache coherence protocols based on <jats:italic>state enumeration, (symbolic model checking</jats:italic> , and <jats:italic>symbolic state models</jats:italic> . Since these techniques search the state space of the protocol exhaustively, the amount of memory required to manipulate that state information and the verification time grow very fast with the number of processors and the complexity of the protocol mechanisms. To be successful for systems of arbitrary complexity, a verification technique must solve this so-called <jats:italic>state space explosion</jats:italic> problem. The emphasis of our discussion is onthe underlying theory in each method of handling the state space exposion problem, and formulationg and checking the <jats:italic>safety</jats:italic> properties (e.g., data consistency) and the <jats:italic>liveness</jats:italic> properties (absence of deadlock and livelock). We compare the efficiency and discuss the limitations of each technique in terms of memory and computation time. Also, we discuss issues of <jats:italic>generality, applicability, automaticity, and amenity</jats:italic> for existing tools in each class of methods. No method is truly superior because each method has its own strengths and weaknesses. Finally, refinements that can further reduce the verification time and/or the memory requirement are also discussed. </jats:p>

<jats:p>As the gap between processor and memory speeds continues to widen, methods for evaluating memory system designs before they are implemented in hardware are becoming increasingly important. One such method, trace-driven memory simulation, has been the subject of intense interest among researchers and has, as a result, enjoyed rapid development and substantial improvements during the past decade. This article surveys and analyzes these developments by establishing criteria for evaluating trace-driven methods, and then applies these criteria to describe, categorize, and compare over 50 trace-driven simulation tools. We discuss the strengths and weaknesses of different approaches and show that no single method is best when all criteria, including accuracy, speed, memory, flexibility, portability, expense, and ease of use are considered. In a concluding section, we examine fundamental limitations to trace-driven simulation, and survey some recent developments in memory simulation that may overcome these bottlenecks.</jats:p>