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Modern Circuit Placement: Best Practices and Results

Gi-Joon Nam ; Jason Cong (eds.)

Resumen/Descripción – provisto por la editorial

No disponible.

Palabras clave – provistas por la editorial

Circuits and Systems; Electrical Engineering

Disponibilidad
Institución detectada Año de publicación Navegá Descargá Solicitá
No detectada 2007 SpringerLink

Información

Tipo de recurso:

libros

ISBN impreso

978-0-387-36837-5

ISBN electrónico

978-0-387-68739-1

Editor responsable

Springer Nature

País de edición

Reino Unido

Fecha de publicación

Información sobre derechos de publicación

© Springer-Verlag US 2007

Tabla de contenidos

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs

Tung-Chieh Chen; Zhe-Wei Jiang; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang

This chapter is focused on NTUplace3 [6], a large-scale mixed-size analytical placer that can handle modern placement considerations such as wirelength, preplaced blocks, and density. Like many modern placers, NTUplace3 consists of three major stages: global placement, legalization, and detailed placement. Global placement evenly distributes blocks and finds the best position for each block to minimize the target cost (e.g., wirelength). Then, legalization removes all overlaps among blocks and places standard cells row by row. Detailed placement further refines the solution.

Palabras clave: Conjugate Gradient; Benchmark Suite; Base Potential; Placement Region; Empty Slot.

4 - Multilevel Placement Techniques | Pp. 289-309

Conclusion and Challenges

Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly optimize the interconnects, which have become the bottleneck in circuit and system performance in the nanometer process technologies.

4 - Multilevel Placement Techniques | Pp. 311-312