Catálogo de publicaciones - libros

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip (SOC) designs. A new chip design paradigm called Network-on-Chip (NOC) offers a promising architectural choice for future SOC. Focusing on decreasing node degree, reducing links and shortening diameter, a new NOC, named Triple-based Hierarchical Interconnection Network (THIN), is presented in this paper. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. The network properties and zero-load latency were studied and compared with 2-D mesh and Hypercube. The results show THIN is superior to 2-D mesh and Hypercube to construct interconnection network for SOC, when the network size is not very large. A new tree-based multicast routing algorithm in THIN is proposed. Thorough analyses and experiments based on different multicast implementation schemes are conducted. The results do confirm the advantage of our scheme over unicast-based and path-based multicast schemes.

Spam is commonly defined as unsolicited email messages and the goal of spam filtering is to distinguish between spam and legitimate email messages. Much work has been done to filter spam from legitimate emails using machine learning algorithm and substantial performance has been achieved with some amount of false positive (FP) tradeoffs. In the case of spam detection FP problem is unacceptable sometimes. In this paper, an adaptive spam filtering model has been proposed based on Machine learning (ML) algorithms which will get better accuracy by reducing FP problems. This model consists of individual and combined filtering approach from existing well known ML algorithms. The proposed model considers both individual and collective output and analyzes them by an analyzer. A dynamic feature selection (DFS) technique also proposed in this paper for getting better accuracy.

Border Gateway Protocol (BGP) is the de facto inter-domain routing protocol. With the rapid development of the Internet, the convergence problem of BGP attracts more attention. This paper analyzes the relationship between BGP convergence and the characteristics of the Internet. The Internet is classified into three hierarchies based on the power-law and commercial relations of autonomous systems. The relation of network topology and BGP convergence performance is presented for all sorts of convergence events in different layers. The result shows that the power-law nature of network influences the BGP convergence greatly. So we present a new proposal to improve BGP convergence based on power-law, called “best up”, which behaves better than normal convergence mode in the experiments.

In this paper, several diffusion schemes, designed for load balancing on optical transpose interconnection system (OTIS), have been generalized to heterogeneous OTIS-networks,based on an ideal of divide and conquer. These generalized schemes are called GDED-X and they schedule the load flow on intragroup links and intergroup links separately. Contrasted with other existing schemes available to heterogeneous networks, GDED-X schemes have a prominent promotion in efficiency and stability of iteration. Some theoretical evidences and experimental results are also be given to show that GDED-X schemes are better than those traditional X schemes for heterogeneous OTIS-networks, which shows the usability of our proposed schemes.

The problem of scheduling a weighted directed acyclic graph (DAG) representing an application to a set of heterogeneous processors to minimize the completion time has been recently studied. The NP-completeness of the problem has instigated researchers to propose different heuristic algorithms. In this paper, we present a Generalized Critical-task Anticipation () algorithm for DAG scheduling in heterogeneous computing environment. The scheduling algorithm employs task prioritizing technique based on algorithm and introduces a new processor selection scheme by considering heterogeneous communication costs among processors for adapting grid and scalable computing. To evaluate the performance of the proposed technique, we have developed a simulator that contains a parametric graph generator for generating weighted directed acyclic graphs with various characteristics. We have implemented the algorithm along with the and scheduling algorithms on the simulator. The algorithm is shown to be effective in terms of speedup and low scheduling costs.