Catálogo de publicaciones - libros

Extremely down-scaled field effect transistor, innovative manufacturing of semiconductors, novel material and computing devices have led to rapid changes in the semiconductor industry which now allows more complex systems and more computing power per chip area than several years ago. Albeit these significant improvements novel technology nodes also offer unsolved problems to researchers and challenges to the designers. In this paper, we give a brief overview about actual trends and problems in the semiconductor industry and how the upcoming tasks can be solved by the designers and researchers.

In future nanotechnologies failure densities are predicted to be several orders of magnitude higher than in current CMOS technologies. For such failure densities existing fault tolerance implementations are inadequate. This work presents several principles of building multiple-fault tolerant memory cells and logic gates for circuits affected by high defect densities as well as a first evaluation of the area cost and performance.

A generic programmable time event coded circuit which forms the building block for a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems 0.35 m CMOS technology to demonstrate the functionality of the circuits in silicon.

We have designed an adaptive analogue VLSI neuromorphic chip that will be used to interface MEM wind sensors to an insect-inspired robot. The main chip components are a sensory interface circuit to amplify the signal from the MEM device, and integrate and fire neurons with adaptive firing thresholds. The chip has been implemented using Austria Microsystem System’s 0.35 CMOS technology. We report the response of the prototype sensor to a wind stimulus, and show the neural circuit can reproduce the adaptive behaviour of biological sensory neurons.

In this paper, the implementation results of an integrate and fire neuron implemented in a 130 nm process are presented. This publication covers the properties of IAF neurons from calculations on an ideal electrical circuit modeling the soma of an IAF neuron and compares the theoretical results with simulation results from an extracted layout of the implemented neuron.

A standard Full-Adder (FA) and an FA based on threshold logic exploiting the ”mirrored gate”, implemented in a standard 90 nm CMOS technology, are shown not to withstand statistical mismatch and process variations for supply voltages below 150 mV. Exploiting a redundancy scheme tolerating ”open” faults, with gate level redundancy and shorted outputs, shows that the same two FAs might produce adequate Sum and Carry outputs at the presence of a defect PMOS for supply voltages above 150 mV, for a redundancy factor of 2. Two additional threshold gates do not tolerate the process variations, according to simulations. Simulations suggest that the standard FA has the lowest power consumption. Power consumption varies more than an order of magnitude for all subthreshold FAs, due to the statistical variations.

Graphics Processing Units (GPUs) have evolved into powerful programmable processors, faster than Central Processing Units (CPUs) regarding the execution of parallel algorithms. In this paper, an implementation of a Fuzzy ART Neural Network on the GPU is presented. Experimental results show training process is slower on the GPU than on a dual-core Pentium 4 at 3.2 GHz. Once the Neural Network has been trained, the proposed design manages to accelerate Fuzzy ART testing process up to 33 times on a GeForce 7800GT graphics card.

This paper presents a network architecture to interconnect mixed-signal VLSI integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. The architecture uses isochronous connections to reserve network bandwidth and is optimized for the small data event packets that have to be exchanged in spiking hardware neural networks. End-to-end delay is reduced to the minimum by retaining 100% throughput. As buffering is avoided wherever possible, the resulting jitter is independent of the number of neural network chips used. This allows to experiment with neural networks of thousands of artificial neurons with a speedup of up to 10 compared to biology. Simulation results are presented. The work focuses on the interconnection of hardware neural networks. In addition to this, the proposed architecture is suitable for any application where bandwidth requirements are known and constant low delay is needed.

This paper presents configuration methods for an existing neuromorphic hardware and shows first experimental results. The utilized mixed-signal VLSI device implements a highly accelerated network of integrate-and-fire neurons. We present a software framework, which provides the possibility to interface the hardware and explore it from the point of view of neuroscience. It allows to directly compare both spike times and membrane potentials which are emulated by the hardware or are computed by the software simulator NEST, respectively, from within a single software scope. Membrane potential and spike timing dependent plasticity measurements are shown which illustrate the capabilities of the software framework and document the functionality of the chip.

This paper presents an exact reliability analysis of von Neumann multiplexing using majority gates of fan-in Δ = 3, 5, 7, 9, 11, and the corresponding minimum redundancy factors = 6, 10, 14, 18, 22. Such results are extremely important for a deeper understanding of von Neumann multiplexing (and its variations), especially when considering the expected unreliable behavior of future nano-devices and interconnects. The analysis confirms and augments well-known theoretical results, and is exact as being obtained using exhaustive counting. The extension of the analysis to the device level will allow us to characterize von Neumann multiplexing with respect to device failures for the first time. The results are very timely and are also explaining a strange (non-linear) behavior of von Neuman multiplexing reported two years ago (based on extensive Monte Carlo simulations).