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Guide to RISC Processors: for Programmers and Engineers

Sivarama P. Dandamudi

Resumen/Descripción – provisto por la editorial

No disponible.

Palabras clave – provistas por la editorial

Processor Architectures; Control Structures and Microprogramming; Software Engineering/Programming and Operating Systems; Computer Systems Organization and Communication Networks; Programming Techniques

Disponibilidad
Institución detectada Año de publicación Navegá Descargá Solicitá
No detectada 2005 SpringerLink

Información

Tipo de recurso:

libros

ISBN impreso

978-0-387-21017-9

ISBN electrónico

978-0-387-27446-1

Editor responsable

Springer Nature

País de edición

Reino Unido

Fecha de publicación

Información sobre derechos de publicación

© Springer Science+Business Media, Inc. 2005

Cobertura temática

computacion

Ciencias de la computación e información

artes

Artes

Tabla de contenidos

doi: 10.1007/0-387-27446-4_1

Introduction

Part I - Overview | Pp. 3-11

doi: 10.1007/0-387-27446-4_2

Processor Design Issues

Palabras clave: Procedure Call; Program Counter; Target Address; Conditional Branch; Branch Prediction.

Part I - Overview | Pp. 13-37

doi: 10.1007/0-387-27446-4_3

RISC Principles

Part I - Overview | Pp. 39-44

doi: 10.1007/0-387-27446-4_4

MIPS Architecture

Part II - Architectures | Pp. 47-54

doi: 10.1007/0-387-27446-4_5

SPARC Architecture

Palabras clave: Condition Code; Target Address; Register Window; Branch Instruction; RISC Processor.

Part II - Architectures | Pp. 55-77

doi: 10.1007/0-387-27446-4_6

PowerPC Architecture

Palabras clave: Load Instruction; Target Address; Count Register; Branch Instruction; RISC Processor.

Part II - Architectures | Pp. 79-96

doi: 10.1007/0-387-27446-4_7

Itanium Architecture

Palabras clave: Instruction Group; Procedure Call; Load Instruction; Target Address; Speculative Execution.

Part II - Architectures | Pp. 97-120

doi: 10.1007/0-387-27446-4_8

ARM Architecture

Palabras clave: Condition Code; Program Counter; Index Register; Branch Instruction; RISC Processor.

Part II - Architectures | Pp. 121-145

doi: 10.1007/0-387-27446-4_9

SPIM Simulator and Debugger

Palabras clave: Simulator Setting; RISC Processor; Symbol Table; Command Line Option; Assembly Language Program.

Part III - MIPS Assembly Language | Pp. 149-157

doi: 10.1007/0-387-27446-4_10

Assembly Language Overview

Part III - MIPS Assembly Language | Pp. 159-182