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This book makes a case as to why programmable platforms will enable the next design discontinuity. In particular we argue that system designers looking to realize system applications will increasingly eschew ASICs designed through an HDL-based synthesis methodology for programmable platforms. These programmable platforms are themselves assemblages of programmable components. Chris Rowen, Tensilica’s founder and CEO, has been quoted as saying: “The processor is the NAND gate of the future.” We paraphrase this to say: “ASIPs are the standard-cells of the future.” Both the gate-level design era of the 1980’s and the register-transfer level design era of the 1990’s relied heavily on well-designed standard cells. Similarly, we anticipate that the next design discontinuity will rely heavily on well-designed ASIPs as basic building blocks. However, we believe that the future success of ASIPs will depend on developing high-productivity design methodologies for ASIPs that produce efficient designs. Describing such a methodology is the goal of this book.

In this chapter we have reviewed existing benchmarking efforts and revealed flaws why they cannot be applied to benchmarking of whole systems. We have derived four principles of a generalized benchmarking methodology considering heterogeneous system architectures:

The methodology defines a template for a benchmark consisting of functional, environment, and measurement specifications. As an illustrative example, we have tailored this methodology to the specific requirements and goals of network processor benchmarking. However, other application domains (e.g. telecommunications, multimedia, automotive) also benefit from this work.

Our key contributions, illustrated for network processing, are the emphasis of the system-level interfaces for NPUs based on our line card model, the utility of a Click executable description, motivation for application-level benchmarks, and a disciplined approach to identifying a set of benchmarks. In summary, we believe we have identified key issues in benchmarking ASIPs as well as programmable platforms and embodied them in a methodology for judiciously using benchmarking.

Many beautiful results on the value-distribution of -functions follow from the general theory of Dirichlet series like the Big Picard theorem (see Boas [26] and Mandelbrojt [234]), but more advanced statements can only be proved by exploiting the characterizing properties (the functional equation and the Euler product). In this chapter, we study the distribution of values of Dirichlet series satisfying a Riemann-type functional equation. These results are due to Steuding [346, 347] and their proofs follow in the main part the methods of Levinson [217], Levinson and Montgomery [218], and Nevanlinna theory.

In this chapter we have reviewed existing benchmarking efforts and revealed flaws why they cannot be applied to benchmarking of whole systems. We have derived four principles of a generalized benchmarking methodology considering heterogeneous system architectures:

The methodology defines a template for a benchmark consisting of functional, environment, and measurement specifications. As an illustrative example, we have tailored this methodology to the specific requirements and goals of network processor benchmarking. However, other application domains (e.g. telecommunications, multimedia, automotive) also benefit from this work.

Our key contributions, illustrated for network processing, are the emphasis of the system-level interfaces for NPUs based on our line card model, the utility of a Click executable description, motivation for application-level benchmarks, and a disciplined approach to identifying a set of benchmarks. In summary, we believe we have identified key issues in benchmarking ASIPs as well as programmable platforms and embodied them in a methodology for judiciously using benchmarking.

Many beautiful results on the value-distribution of -functions follow from the general theory of Dirichlet series like the Big Picard theorem (see Boas [26] and Mandelbrojt [234]), but more advanced statements can only be proved by exploiting the characterizing properties (the functional equation and the Euler product). In this chapter, we study the distribution of values of Dirichlet series satisfying a Riemann-type functional equation. These results are due to Steuding [346, 347] and their proofs follow in the main part the methods of Levinson [217], Levinson and Montgomery [218], and Nevanlinna theory.

In this chapter we have reviewed existing benchmarking efforts and revealed flaws why they cannot be applied to benchmarking of whole systems. We have derived four principles of a generalized benchmarking methodology considering heterogeneous system architectures:

The methodology defines a template for a benchmark consisting of functional, environment, and measurement specifications. As an illustrative example, we have tailored this methodology to the specific requirements and goals of network processor benchmarking. However, other application domains (e.g. telecommunications, multimedia, automotive) also benefit from this work.

Our key contributions, illustrated for network processing, are the emphasis of the system-level interfaces for NPUs based on our line card model, the utility of a Click executable description, motivation for application-level benchmarks, and a disciplined approach to identifying a set of benchmarks. In summary, we believe we have identified key issues in benchmarking ASIPs as well as programmable platforms and embodied them in a methodology for judiciously using benchmarking.

Many beautiful results on the value-distribution of -functions follow from the general theory of Dirichlet series like the Big Picard theorem (see Boas [26] and Mandelbrojt [234]), but more advanced statements can only be proved by exploiting the characterizing properties (the functional equation and the Euler product). In this chapter, we study the distribution of values of Dirichlet series satisfying a Riemann-type functional equation. These results are due to Steuding [346, 347] and their proofs follow in the main part the methods of Levinson [217], Levinson and Montgomery [218], and Nevanlinna theory.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.