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<jats:title>Abstract</jats:title> <jats:p>Herein, we propose a high-quality (<jats:italic>Q</jats:italic>) factor hybrid plasmonic nanocavity based on distributed Bragg reflectors (DBRs) with low propagation loss and extremely strong mode confinement. This hybrid plasmonic nanocavity is composed of a high-index cylindrical nanowire separated from a metal surface possessing shallow DBRs gratings by a sufficiently thin low-index dielectric layer. The hybrid plasmonic nanocavity possesses advantages such as a high Purcell factor (<jats:italic>F</jats:italic> <jats:sub>p</jats:sub>) of up to nearly 20000 and a gain threshold approaching 266 cm<jats:sup>−1</jats:sup> at 1550 nm, promising a greater potential in deep sub-wavelength lasing applications.</jats:p>

<jats:title>Abstract</jats:title> <jats:p>Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 10<jats:sup>11</jats:sup>/cm<jats:sup>2</jats:sup>) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.</jats:p>