Catálogo de publicaciones - libros

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.

The MESCAL methodology and the Tensilica configurable-processor-core design approach agree on the importance of processors as the key flexible building block for SoC designs, making it possible to leverage the very high transistor count and excellent connectivity made available by nanometer silicon lithography with relatively little manual design effort. Configurable processor cores or ASIPs can achieve much higher performance than conventional, fixed-ISA processors through the addition of custom-tailored execution units, registers and register files, and specialized communication interface ports.

The disciplined MESCAL five-element methodology is easily supported by the capabilities of Tensilica’s design approach. New technologies such as automated processor design-space exploration help to automate elements of the process that would typically rely on manual application. Tensilica’s capabilities for heterogeneous inter-processor communication mechanisms demonstrate how the MESCAL methodology can be extended to include the creation of increasingly complex application-oriented MP subsystems.

Such a methodology could include more abstract application-task partitioning and communication programmer’s models, which can be flexibly mapped onto heterogeneous sets of MP communications resources including combinations of direct connections, FIFO queues, shared memory, and bus-based architectures. If a designer starts with application code that utilizes communications abstractions, he or she can then map the high level “virtual channels” onto a variety of physical implementation forms. The use of simulation, and cost estimators to analyze the various alternatives, creates an automated “communications-space exploration” design flow which shifts attention from individual processors to the MP subsystem as a whole.

Of course, applications implemented with an MPSoC subsystem can then drive automated processor optimization and system balancing (both processing and communications) using technologies such as the XPRES™ compiler. The combination of an abstract communications model at the application level, automated mapping, processor and communications implementation generation, and design-space exploration, represents a new level in MPSoC system design automation, and elevates the MESCAL methodology to a new level.